soc/intel/quark: Pass serial port address to FSP
Pass the serial port address to FSP using a UPD value in the MemoryInit API. TEST=Build and run on Galileo Gen2 Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15079 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -132,6 +132,24 @@ void soc_memory_init_params(struct romstage_params *params,
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printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
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reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
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}
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/* Update the UPD data for MemoryInit */
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printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd);
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upd->PcdSerialRegisterBase = UART_BASE_ADDRESS;
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upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
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config->PcdSmmTsegSize : 0;
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}
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void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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MEMORY_INIT_UPD *new)
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{
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/* Display the parameters for MemoryInit */
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printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
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fsp_display_upd_value("PcdSerialRegisterBase",
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sizeof(old->PcdSerialRegisterBase),
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old->PcdSerialRegisterBase, new->PcdSerialRegisterBase);
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fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize),
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old->PcdSmmTsegSize, new->PcdSmmTsegSize);
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}
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void soc_after_ram_init(struct romstage_params *params)
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@ -157,8 +175,3 @@ void soc_after_ram_init(struct romstage_params *params)
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/* Initialize the PCIe bridges */
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pcie_init();
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}
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void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
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MEMORY_INIT_UPD *new)
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{
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}
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@ -77,39 +77,39 @@ typedef struct {
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typedef struct {
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/** Offset 0x0020
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/** Offset 0x0018
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**/
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UINT64 Signature;
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/** Offset 0x0028
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/** Offset 0x0020
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**/
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UINT64 Revision;
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/** Offset 0x0030
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/** Offset 0x0028
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**/
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UINT32 PcdRmuBinaryBaseAddress;
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/** Offset 0x002C
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**/
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UINT32 UnusedUpdSpace0;
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/** Offset 0x0030
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**/
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UINT32 PcdSerialRegisterBase;
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/** Offset 0x0034
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**/
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UINT32 PcdRmuBinaryLen;
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/** Offset 0x0038
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**/
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UINT8 PcdSmmTsegSize;
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/** Offset 0x0039
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/** Offset 0x0035
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**/
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UINT8 PcdPlatformType;
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/** Offset 0x003A
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**/
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UINT8 ReservedMemoryInitUpd[22];
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UINT8 ReservedMemoryInitUpd[3];
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} MEMORY_INIT_UPD;
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typedef struct {
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/** Offset 0x0050
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/** Offset 0x0038
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**/
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UINT64 Signature;
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/** Offset 0x0058
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/** Offset 0x0040
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**/
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UINT64 Revision;
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/** Offset 0x0060
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/** Offset 0x0048
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**/
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UINT8 ReservedSiliconInitUpd[32];
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UINT16 PcdRegionTerminator;
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} SILICON_INIT_UPD;
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#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
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@ -130,17 +130,11 @@ typedef struct _UPD_DATA_REGION {
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**/
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UINT32 SiliconInitUpdOffset;
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/** Offset 0x0018
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**/
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UINT64 ReservedUpd1;
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/** Offset 0x0020
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**/
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MEMORY_INIT_UPD MemoryInitUpd;
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/** Offset 0x0050
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/** Offset 0x0038
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**/
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SILICON_INIT_UPD SiliconInitUpd;
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/** Offset 0x0080
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**/
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UINT16 PcdRegionTerminator;
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} UPD_DATA_REGION;
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#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
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