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imgtec/pistachio: DDR2, DDR3: DLL reset set 

Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.

Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.

Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ionela Voinescu 2015-05-26 12:20:19 +01:00 committed by Martin Roth
parent 6b95406ff3
commit 721f2998a5
2 changed files with 2 additions and 2 deletions
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2
src/soc/imgtec/pistachio/ddr2_init.c
View File

@ -112,7 +112,7 @@ int init_ddr2(void)
* 15:13 RSVD RSVD * 15:13 RSVD RSVD
* 31:16 Reserved * 31:16 Reserved
*/ */
write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0)); write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
/* MR1 : EMR Register /* MR1 : EMR Register
* Generate to use with PHY and PCTL * Generate to use with PHY and PCTL
* 0 DE DLL Enable 0 Disable 1 * 0 DE DLL Enable 0 Disable 1

2
src/soc/imgtec/pistachio/ddr3_init.c
View File

@ -119,7 +119,7 @@ int init_ddr3(void)
* 15:13 RSVD RSVD * 15:13 RSVD RSVD
* 31:16 Reserved * 31:16 Reserved
*/ */
write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001420); write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
/* MR1 : DDR3 mode register 1 /* MR1 : DDR3 mode register 1
* Generate to use with PHY and PCTL * Generate to use with PHY and PCTL
* 0 DE DLL Enable 0 Disable 1 * 0 DE DLL Enable 0 Disable 1