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exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420 

This changes the number of chip selects that we configure from 2 to 1.
On current setups with (x16 memory 4Gbit chips) that means that we're
at 2GByte.

Technically we should add a second setting in the ares_ddr3_timings
and select between the two of the based on board strappings.  That
would make the CONFIG_RUN_TIME_BANK_NUMBER work properly.  I've
changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not
actually doing the board strapping read right now.

This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G
systems will no longer put the system in a messed up state (leading to
a hang).  It also prevents some of the weird boot behavior that we've
seen that comes and goes depending on U-Boot alignment.  See
<http://crosbug.com/p/20577>.

This patch was ported from: https://gerrit.chromium.org/gerrit/66117
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d
Reviewed-on: https://chromium-review.googlesource.com/167210
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6612
Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks 2013-08-23 15:25:07 -07:00 committed by Isaac Christensen
parent dd1aab95a6
commit 72a4288650
2 changed files with 24 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View File

@ -44,7 +44,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
struct exynos5_dmc *drex0, *drex1;
struct exynos5_tzasc *tzasc0, *tzasc1;
u32 val, nLockR, nLockW_phy0, nLockW_phy1;
int i;
int i, chip;
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
@ -218,12 +218,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
* Send auto refresh command for DRAM refresh.
*/
for (i = 0; i < 128; i++) {
writel(DIRECT_CMD_REFA, &drex0->directcmd);
writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(DIRECT_CMD_REFA, &drex1->directcmd);
writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
}
}
@ -263,10 +265,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(nLockR, &phy1_ctrl->phy_con12);
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
writel(val, &drex0->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
@ -316,10 +320,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(0, &phy1_ctrl->phy_con14);
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
writel(val, &drex0->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
writel(val, &drex1->directcmd);
writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
/* Common Settings for Leveling */
val = PHY_CON12_RESET_VAL;

6
src/mainboard/google/pit/memory.c
View File

@ -86,7 +86,7 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
DMC_MEMCONTROL_MEM_TYPE_DDR3 |
DMC_MEMCONTROL_MEM_WIDTH_32BIT |
DMC_MEMCONTROL_NUM_CHIP_2 |
DMC_MEMCONTROL_NUM_CHIP_1 |
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
@ -104,8 +104,8 @@ const struct mem_timings mem_timings = {
DMC_CONCONTROL_AREF_EN_DISABLE |
DMC_CONCONTROL_IO_PD_CON_DISABLE,
.dmc_channels = 1,
.chips_per_channel = 2,
.chips_to_configure = 2,
.chips_per_channel = 1,
.chips_to_configure = 1,
.send_zq_init = 1,
.gate_leveling_enable = 1,
};