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Now bimini can boot linux to login. 

Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
   smp_write_config_table will run. Then intr_data will be written
   into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
   pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
   The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2011-01-21 08:46:27 +00:00 committed by Zheng Bao
parent ba185722d4
commit 72cc87fba5
4 changed files with 10 additions and 10 deletions
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5
src/mainboard/amd/bimini_fam10/Kconfig
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@ -16,18 +16,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select GENERATE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
select TINY_BOOTBLOCK
select GFXUMA
select HAVE_DEBUG_CAR
select SET_FIDVID

3
src/southbridge/amd/sb800/bootblock.c
View File

@ -36,8 +36,7 @@ static void sb800_enable_rom(void)
u8 reg8;
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SB800_LPC), 0);
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_read_config8(dev, 0x48);

10
src/southbridge/amd/sb800/early_setup.c
View File

@ -65,6 +65,8 @@ static void sb800_acpi_init(void) {
* the contents of the PM registers at
* index 60-6B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/
/* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
}
/* RPR 2.28 Get SB ASIC Revision.*/
@ -568,11 +570,11 @@ static void sb800_pci_cfg(void)
byte |= (1 << 3);
pci_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
/* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pmio_read(0x65);
byte |= (1 << 4);
pmio_write(0x65, byte);
byte = pmio_read(0xF0);
byte |= (1 << 2);
pmio_write(0xF0, byte);
/* IDE Device, BDF:0-20-1 */
dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0);

2
src/southbridge/amd/sb800/fadt.c
View File

@ -38,7 +38,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 3;
header->revision = 1; /* TODO: 3 will make linux hang. */
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4);