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soc/intel/skylake: Move PMC MMIO offset macro into pmc.h 

This patch ensures PMC offset 0xfc resides into pmc.h rather defining
into p2sb.h.

Change-Id: Iae1c38beae15355a077be80112b723b8ad3d0a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45800
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-28 21:03:27 +05:30
parent 063e933194
commit 7335225600
2 changed files with 1 additions and 2 deletions
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2
src/soc/intel/skylake/include/soc/p2sb.h
View File

@ -11,6 +11,4 @@
#define PCH_P2SB_EPMASK0 0xB0 #define PCH_P2SB_EPMASK0 0xB0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC
#endif /* _SOC_P2SB_H_ */ #endif /* _SOC_P2SB_H_ */

1
src/soc/intel/skylake/include/soc/pmc.h
View File

@ -77,6 +77,7 @@
#define DSX_EN_LAN_WAKE_PIN (1 << 0) #define DSX_EN_LAN_WAKE_PIN (1 << 0)
#define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_TPR_CFG 0xc4
#define PMSYNC_LOCK (1 << 31) #define PMSYNC_LOCK (1 << 31)
#define PCH_PWRM_ACPI_TMR_CTL 0xfc
#define GPIO_GPE_CFG 0x120 #define GPIO_GPE_CFG 0x120
#define GPE0_DWX_MASK 0xf #define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4*(x)) #define GPE0_DW_SHIFT(x) (4*(x))