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mainboard/intel/glkrvp: configure RAPL PL1 for GLK 

Sets RAPL PL1 power to ~6W.

Note: 7.5W setting gives a run-time 6W actual measured power.

Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.

Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cole Nelson 2017-05-18 15:39:22 -07:00 committed by Aaron Durbin
parent d59f62bbda
commit 735779cc9a
1 changed files with 2 additions and 4 deletions
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6
src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
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@ -55,10 +55,8 @@ chip soc/intel/apollolake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# PL1 override 12000 mW: the energy calculation is wrong with the # PL1 override: 7.5W setting gives a run-time 6W actual
# current VR solution. Experiments show that SoC TDP max (6W) can register "tdp_pl1_override_mw" = "7500"
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Set RAPL PL2 to 15W. # Set RAPL PL2 to 15W.
register "tdp_pl2_override_mw" = "15000" register "tdp_pl2_override_mw" = "15000"