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soc/intel/alderlake: Fix incorrect microcode comments 

The microcode for RPL-S C0 and H0 is actually available, however, the
name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos
in the comments.

Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256
sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256
sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag
microcode-20230808:

5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9

Update the comments to correctly indicate supported CPU steppings.

Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2023-10-16 15:32:59 +02:00
parent fa78ecacec
commit 7357f2a0ff
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/Makefile.inc
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@ -78,11 +78,11 @@ endif
ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples
# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples
# ADL-S/HX C0 and ADL-S H0
# 06-b7-00 are RPL-S Engineering Samples
# ADL-S/HX C0/H0 and RPL-S C0/H0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
# RPL-S/HX B0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01
# 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing
else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00
else