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AGESA: Add romstage timestamps 

Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.

Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-07-17 23:00:31 +03:00
parent fb32be4090
commit 7369e83de1
1 changed files with 10 additions and 0 deletions
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10
src/cpu/amd/agesa/romstage.c
View File

@ -26,6 +26,7 @@
#include <romstage_handoff.h>
#include <smp/node.h>
#include <string.h>
#include <timestamp.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
@ -60,6 +61,9 @@ void * asmlinkage romstage_main(unsigned long bist)
if ((initial_apic_id == 0) && boot_cpu()) {
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
platform_once(cb);
console_init();
@ -77,11 +81,17 @@ void * asmlinkage romstage_main(unsigned long bist)
agesa_execute_state(cb, AMD_INIT_EARLY);
timestamp_add_now(TS_BEFORE_INITRAM);
if (!cb->s3resume)
agesa_execute_state(cb, AMD_INIT_POST);
else
agesa_execute_state(cb, AMD_INIT_RESUME);
/* FIXME: Detect if TSC frequency changed during raminit? */
timestamp_rescale_table(1, 4);
timestamp_add_now(TS_AFTER_INITRAM);
} else {
agesa_main(cb);