rk3288: update romstage & mainboard

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723
Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209469
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8867
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/veyron/Kconfig

@@ -42,7 +42,7 @@ config MAINBOARD_VENDOR
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
-	default 1
+	default 0
 
 config BOOT_MEDIA_SPI_BUS
         int

src/mainboard/google/veyron/Makefile.inc

@@ -18,7 +18,10 @@
 ##
 
 romstage-y += romstage.c
+romstage-y += chromeos.c
 romstage-y += sdram_configs.c
+ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += chromeos.c
+ramstage-y += pmic.c
 

src/mainboard/google/veyron/chromeos.c

@@ -23,11 +23,68 @@
 #include <ec/google/chromeec/ec_commands.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <soc/rockchip/rk3288/gpio.h>
 
+#define GPIO_WP		(gpio_t){.port = 7, .bank = GPIO_A, .idx = 6}
+#define GPIO_LID	(gpio_t){.port = 7, .bank = GPIO_B, .idx = 5}
+#define GPIO_POWER	(gpio_t){.port = 0, .bank = GPIO_A, .idx = 5}
+#define GPIO_RECOVERY	(gpio_t){.port = 0, .bank = GPIO_B, .idx = 1}
+
+void setup_chromeos_gpios(void)
+{
+	gpio_input(GPIO_WP);
+	gpio_input_pullup(GPIO_LID);
+	gpio_input_pullup(GPIO_POWER);
+	gpio_input_pullup(GPIO_RECOVERY);
+}
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
+	int count = 0;
 
+	/* Write Protect: active low */
+	gpios->gpios[count].port = GPIO_WP.raw;
+	gpios->gpios[count].polarity = ACTIVE_LOW;
+	gpios->gpios[count].value = gpio_get_in_value(GPIO_WP);
+	strncpy((char *)gpios->gpios[count].name, "write protect",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Recovery: active low */
+	gpios->gpios[count].port = GPIO_RECOVERY.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[count].name, "recovery",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Lid: active high */
+	gpios->gpios[count].port = GPIO_LID.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = gpio_get_in_value(GPIO_LID);
+	strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Power:GPIO active high */
+	gpios->gpios[count].port = GPIO_POWER.raw;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = gpio_get_in_value(GPIO_POWER);
+	strncpy((char *)gpios->gpios[count].name, "power",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	/* Developer: GPIO active high */
+	gpios->gpios[count].port = -1;
+	gpios->gpios[count].polarity = ACTIVE_HIGH;
+	gpios->gpios[count].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[count].name, "developer",
+		GPIO_MAX_NAME_LENGTH);
+	count++;
+
+	gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+	gpios->count = count;
+
+	printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
 }
 
 int get_developer_mode_switch(void)
@@ -37,10 +94,19 @@ int get_developer_mode_switch(void)
 
 int get_recovery_mode_switch(void)
 {
-	return 0;
+	uint32_t ec_events;
+
+	/* The GPIO is active low. */
+	if (!gpio_get_in_value(GPIO_RECOVERY))
+		return 1;
+
+	ec_events = google_chromeec_get_events_b();
+	return !!(ec_events &
+		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
 }
 
 int get_write_protect_state(void)
 {
-	return 0;
+	return !gpio_get_in_value(GPIO_WP);
 }
+

src/mainboard/google/veyron/mainboard.c

@@ -24,10 +24,102 @@
 #include <edid.h>
 #include <vbe.h>
 #include <boot/coreboot_tables.h>
+#include <device/i2c.h>
+#include <soc/rockchip/rk3288/gpio.h>
+#include <soc/rockchip/rk3288/soc.h>
+#include <soc/rockchip/rk3288/pmu.h>
+#include <soc/rockchip/rk3288/clock.h>
+#include <soc/rockchip/rk3288/spi.h>
+#include "pmic.h"
+
+#define DRAM_START	(CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_SIZE	CONFIG_DRAM_SIZE_MB
+#define DRAM_END	(DRAM_START + DRAM_SIZE)
+
+static void setup_gpio(void)
+{
+	/*SOC and TPM reset GPIO, active high.*/
+	gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 2}, 0);
+
+	/* Configure GPIO for lcd_bl_en */
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 2}, 1);
+
+	/*Configure backlight PWM 100% brightness*/
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 0}, 0);
+
+	/* Configure GPIO for lcd_en */
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 7}, 1);
+}
+
+static void setup_iomux(void)
+{
+	/*i2c0 for pmic*/
+	setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
+	setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
+
+	/*i2c1 for tpm*/
+	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+
+	/*i2c2 for codec*/
+	writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
+
+	writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+	writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
+	writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+	writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+	writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+	writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
+	writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
+	writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+}
+
+static void setup_usb_poweron(void)
+{
+	/* Configure GPIO for usb1_pwr_en */
+	gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 3}, 1);
+
+	/* Configure GPIO for usb2_pwr_en */
+	gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 4}, 1);
+
+	/* Configure GPIO for 5v_drv */
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 3}, 1);
+}
+
+static void configure_sdmmc(void)
+{
+	/* Configure GPIO for sd_en */
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_C, .idx = 5}, 1);
+
+	/* Configure GPIO for sd_detec */
+	gpio_input_pullup((gpio_t){.port = 7, .bank = GPIO_A, .idx = 5});
+
+	/*use sdmmc0 io, disable JTAG function*/
+	writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+}
+
+static void configure_emmc(void)
+{
+	/* Configure GPIO for emmc_pwrctrl */
+	gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 4}, 1);
+}
+
+static void configure_i2s(void)
+{
+	/*AUDIO IO domain 1.8V voltage selection*/
+	writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+	rkclk_configure_i2s(12288000);
+}
 
 static void mainboard_init(device_t dev)
 {
-
+	setup_iomux();
+	pmic_init(0);
+	setup_gpio();
+	setup_usb_poweron();
+	configure_sdmmc();
+	configure_emmc();
+	configure_i2s();
+	rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
 }
 
 static void mainboard_enable(device_t dev)

src/mainboard/google/veyron/pmic.c

@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include "pmic.h"
+
+#define RK808_ADDR	0x1b
+#define LOD1EN		(1 << 0)
+#define LOD2EN		(1 << 1)
+#define LOD3EN		(1 << 2)
+#define LOD4EN		(1 << 3)
+#define LOD5EN		(1 << 4)
+#define LOD6EN		(1 << 5)
+#define LOD7EN		(1 << 6)
+#define LOD8EN		(1 << 7)
+
+#define LDO_BASE18V	18
+#define LDO_BASE08V	8
+#define LDOVSEL(mV, base) (mV/100 - base)
+
+struct rk808_reg {
+	 u8 reg;
+	 u8 val;
+};
+
+enum {
+	 LDO_EN = 0x24,
+	 LDO1_ONSEL = 0x3B,
+	 LDO1_SLPSEL,
+	 LDO2_ONSEL,
+	 LDO2_SLPSEL,
+	 LDO3_ONSEL,
+	 LDO3_SLPSEL,
+	 LDO4_ONSEL,
+	 LDO4_SLPSEL,
+	 LDO5_ONSEL,
+	 LDO5_SLPSEL,
+	 LDO6_ONSEL,
+	 LDO6_SLPSEL,
+	 LDO7_ONSEL,
+	 LDO7_SLPSEL,
+	 LDO8_ONSEL,
+	 LDO8_SLPSEL,
+};
+
+static struct rk808_reg ldo_initlist[] = {
+	 {LDO4_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_lcd*/
+	 {LDO5_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_codec*/
+	 {LDO6_ONSEL, LDOVSEL(1000, LDO_BASE08V)}, /*vcc10_lcd*/
+	 {LDO8_ONSEL, LDOVSEL(3300, LDO_BASE18V)}, /*vccio_sd*/
+};
+
+void pmic_init(unsigned int bus)
+{
+	uint8_t read_reg;
+	int i;
+	for (i = 0; i < ARRAY_SIZE(ldo_initlist); i++) {
+		struct rk808_reg *reg = &ldo_initlist[i];
+		i2c_writeb(bus, RK808_ADDR, reg->reg, reg->val);
+	}
+
+	/*enable ldo4,ldo5,ldo6,ldo8*/
+	i2c_readb(bus, RK808_ADDR, LDO_EN, &read_reg);
+	i2c_writeb(bus, RK808_ADDR, LDO_EN, read_reg | LOD8EN | LOD6EN
+						     | LOD5EN | LOD4EN);
+}

src/mainboard/google/veyron/pmic.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__
+#define __SOC_ROCKCHIP_RK3288_PMIC_H__
+void pmic_init(unsigned int bus);
+#endif

src/mainboard/google/veyron/romstage.c

@@ -27,17 +27,34 @@
 #include <timestamp.h>
 #include <arch/cache.h>
 #include <arch/exception.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/rockchip/rk3288/sdram.h>
+#include <soc/rockchip/rk3288/clock.h>
+#include "timer.h"
 
 void main(void)
 {
-	console_init();
+#if CONFIG_COLLECT_TIMESTAMPS
-
+	uint64_t start_romstage_time;
+	uint64_t before_dram_time;
+	uint64_t after_dram_time;
+	uint64_t base_time = timestamp_get();
+	start_romstage_time = timestamp_get();
+#endif
 	/* used for MMU and CBMEM setup, in MB */
 	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
 	u32 dram_size = CONFIG_DRAM_SIZE_MB;
 	u32 dram_end = dram_start + dram_size;
+
+	console_init();
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = timestamp_get();
+#endif
 	sdram_init(get_sdram_config());
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = timestamp_get();
+#endif
 	mmu_init();
 	/* Device memory below DRAM is uncached. */
 	mmu_config_range(0, dram_start, DCACHE_OFF);
@@ -49,10 +66,18 @@ void main(void)
 	/* The space above DRAM is uncached. */
 	if (dram_end < 4096)
 		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
-	mmu_disable_range(0, 1);
 	dcache_mmu_enable();
 
+	setup_chromeos_gpios();
+
 	cbmem_initialize_empty();
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
 	run_ramstage();
 }

src/soc/rockchip/rk3288/Makefile.inc

@@ -21,14 +21,14 @@ IDBTOOL = util/rockchip/make_idb.py
 
 #bootblock-y += bootblock.c
 bootblock-y += cbmem.c
-bootblock-y += timer.c
-bootblock-y += monotonic_timer.c
-bootblock-y += media.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
+bootblock-y += timer.c
+bootblock-y += monotonic_timer.c
 bootblock-y += clock.c
 bootblock-y += spi.c
+bootblock-y += media.c
 
 romstage-y += cbmem.c
 romstage-y += timer.c

src/soc/rockchip/rk3288/cbmem.c

@@ -19,11 +19,9 @@
 
 #include <stddef.h>
 #include <cbmem.h>
-
+#include "soc.h"
-#define FB_SIZE_MB	4
 void *cbmem_top(void)
 {
-	return (void *)(CONFIG_SYS_SDRAM_BASE +
+	return (void *)(get_fb_base_kb()*KiB);
-			(CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB);
 }
 

src/soc/rockchip/rk3288/clock.c

@@ -339,3 +339,34 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
 		printk(BIOS_ERR, "do not support this spi bus\n");
 	}
 }
+
+static u32 clk_gcd(u32 a, u32 b)
+{
+	while (b != 0) {
+		int r = b;
+		b = a % b;
+		a = r;
+	}
+	return a;
+}
+
+void rkclk_configure_i2s(unsigned int hz)
+{
+	int n, d;
+	int v;
+
+	/* i2s source clock: gpll
+	   i2s0_outclk_sel: clk_i2s
+	   i2s0_clk_sel: divider ouput from fraction
+	   i2s0_pll_div_con: 0*/
+	writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 ,
+			     1 << 15 | 0 << 12 | 1 << 8 | 0 << 0),
+			     &cru_ptr->cru_clksel_con[4]);
+
+	/* set frac divider */
+	v = clk_gcd(GPLL_HZ, hz);
+	n = (GPLL_HZ / v) & (0xffff);
+	d = (hz / v) & (0xffff);
+	assert(hz == GPLL_HZ / n * d);
+	writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]);
+}

src/soc/rockchip/rk3288/clock.h

@@ -31,5 +31,6 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
 void rkclk_configure_ddr(unsigned int hz);
+void rkclk_configure_i2s(unsigned int hz);
 
 #endif	/* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */

src/soc/rockchip/rk3288/timer.h

@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __ROCKCHIP_RK3288_TIMER_H__
+#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__
-#define __ROCKCHIP_RK3288_TIMER_H__
+#define __SOC_ROCKCHIP_RK3288_TIMER_H__
 
 #include "addressmap.h"
 
@@ -40,4 +40,4 @@ static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
 
 void rk3288_init_timer(void);
 
-#endif	/* __ROCKCHIP_RK3288_TIMER_H__ */
+#endif	/* __SOC_ROCKCHIP_RK3288_TIMER_H__ */

src/vendorcode/google/chromeos/chromeos.h

@@ -24,6 +24,9 @@
 #include <stdint.h>
 #include <bootmode.h>
 
+/*for mainboard use only*/
+void setup_chromeos_gpios(void);
+
 /* functions implemented in vbnv.c: */
 int get_recovery_mode_from_vbnv(void);
 int vboot_wants_oprom(void);