rk3288: update romstage & mainboard
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723 Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209469 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
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commit
739df1b2c2
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@ -42,7 +42,7 @@ config MAINBOARD_VENDOR
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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hex
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default 1
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default 0
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config BOOT_MEDIA_SPI_BUS
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config BOOT_MEDIA_SPI_BUS
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int
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int
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@ -18,7 +18,10 @@
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##
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##
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += chromeos.c
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romstage-y += sdram_configs.c
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romstage-y += sdram_configs.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += pmic.c
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@ -23,11 +23,68 @@
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#include <ec/google/chromeec/ec_commands.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <string.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/rockchip/rk3288/gpio.h>
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#define GPIO_WP (gpio_t){.port = 7, .bank = GPIO_A, .idx = 6}
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#define GPIO_LID (gpio_t){.port = 7, .bank = GPIO_B, .idx = 5}
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#define GPIO_POWER (gpio_t){.port = 0, .bank = GPIO_A, .idx = 5}
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#define GPIO_RECOVERY (gpio_t){.port = 0, .bank = GPIO_B, .idx = 1}
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void setup_chromeos_gpios(void)
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{
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gpio_input(GPIO_WP);
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gpio_input_pullup(GPIO_LID);
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gpio_input_pullup(GPIO_POWER);
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gpio_input_pullup(GPIO_RECOVERY);
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}
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void fill_lb_gpios(struct lb_gpios *gpios)
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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{
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int count = 0;
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/* Write Protect: active low */
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gpios->gpios[count].port = GPIO_WP.raw;
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gpios->gpios[count].polarity = ACTIVE_LOW;
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gpios->gpios[count].value = gpio_get_in_value(GPIO_WP);
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strncpy((char *)gpios->gpios[count].name, "write protect",
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* Recovery: active low */
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gpios->gpios[count].port = GPIO_RECOVERY.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[count].name, "recovery",
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* Lid: active high */
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gpios->gpios[count].port = GPIO_LID.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = gpio_get_in_value(GPIO_LID);
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strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
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count++;
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/* Power:GPIO active high */
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gpios->gpios[count].port = GPIO_POWER.raw;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = gpio_get_in_value(GPIO_POWER);
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strncpy((char *)gpios->gpios[count].name, "power",
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GPIO_MAX_NAME_LENGTH);
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count++;
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/* Developer: GPIO active high */
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gpios->gpios[count].port = -1;
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gpios->gpios[count].polarity = ACTIVE_HIGH;
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gpios->gpios[count].value = get_developer_mode_switch();
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strncpy((char *)gpios->gpios[count].name, "developer",
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GPIO_MAX_NAME_LENGTH);
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count++;
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gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
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gpios->count = count;
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printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
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}
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}
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int get_developer_mode_switch(void)
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int get_developer_mode_switch(void)
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@ -37,10 +94,19 @@ int get_developer_mode_switch(void)
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int get_recovery_mode_switch(void)
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int get_recovery_mode_switch(void)
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{
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{
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return 0;
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uint32_t ec_events;
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/* The GPIO is active low. */
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if (!gpio_get_in_value(GPIO_RECOVERY))
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return 1;
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ec_events = google_chromeec_get_events_b();
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return !!(ec_events &
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
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}
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}
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int get_write_protect_state(void)
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int get_write_protect_state(void)
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{
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{
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return 0;
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return !gpio_get_in_value(GPIO_WP);
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}
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}
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@ -24,10 +24,102 @@
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#include <edid.h>
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#include <edid.h>
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#include <vbe.h>
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#include <vbe.h>
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#include <boot/coreboot_tables.h>
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#include <boot/coreboot_tables.h>
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#include <device/i2c.h>
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#include <soc/rockchip/rk3288/gpio.h>
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#include <soc/rockchip/rk3288/soc.h>
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#include <soc/rockchip/rk3288/pmu.h>
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#include <soc/rockchip/rk3288/clock.h>
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#include <soc/rockchip/rk3288/spi.h>
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#include "pmic.h"
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#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
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#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
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#define DRAM_END (DRAM_START + DRAM_SIZE)
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static void setup_gpio(void)
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{
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/*SOC and TPM reset GPIO, active high.*/
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 2}, 0);
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/* Configure GPIO for lcd_bl_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 2}, 1);
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/*Configure backlight PWM 100% brightness*/
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gpio_output((gpio_t){.port = 7, .bank = GPIO_A, .idx = 0}, 0);
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/* Configure GPIO for lcd_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 7}, 1);
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}
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static void setup_iomux(void)
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{
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/*i2c0 for pmic*/
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setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
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setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
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/*i2c1 for tpm*/
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writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
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/*i2c2 for codec*/
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writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2);
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
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writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
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writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
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writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
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writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
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writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
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writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
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}
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static void setup_usb_poweron(void)
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{
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/* Configure GPIO for usb1_pwr_en */
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 3}, 1);
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/* Configure GPIO for usb2_pwr_en */
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gpio_output((gpio_t){.port = 0, .bank = GPIO_B, .idx = 4}, 1);
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/* Configure GPIO for 5v_drv */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 3}, 1);
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}
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static void configure_sdmmc(void)
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{
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/* Configure GPIO for sd_en */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_C, .idx = 5}, 1);
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/* Configure GPIO for sd_detec */
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gpio_input_pullup((gpio_t){.port = 7, .bank = GPIO_A, .idx = 5});
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/*use sdmmc0 io, disable JTAG function*/
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writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
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}
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static void configure_emmc(void)
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{
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/* Configure GPIO for emmc_pwrctrl */
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gpio_output((gpio_t){.port = 7, .bank = GPIO_B, .idx = 4}, 1);
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}
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static void configure_i2s(void)
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{
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/*AUDIO IO domain 1.8V voltage selection*/
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writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
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rkclk_configure_i2s(12288000);
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}
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static void mainboard_init(device_t dev)
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static void mainboard_init(device_t dev)
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{
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{
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setup_iomux();
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pmic_init(0);
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setup_gpio();
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setup_usb_poweron();
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configure_sdmmc();
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configure_emmc();
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configure_i2s();
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
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}
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}
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static void mainboard_enable(device_t dev)
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static void mainboard_enable(device_t dev)
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@ -0,0 +1,85 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "pmic.h"
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#define RK808_ADDR 0x1b
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#define LOD1EN (1 << 0)
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#define LOD2EN (1 << 1)
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#define LOD3EN (1 << 2)
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#define LOD4EN (1 << 3)
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#define LOD5EN (1 << 4)
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#define LOD6EN (1 << 5)
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#define LOD7EN (1 << 6)
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#define LOD8EN (1 << 7)
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#define LDO_BASE18V 18
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#define LDO_BASE08V 8
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#define LDOVSEL(mV, base) (mV/100 - base)
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struct rk808_reg {
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u8 reg;
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u8 val;
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};
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enum {
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LDO_EN = 0x24,
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LDO1_ONSEL = 0x3B,
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LDO1_SLPSEL,
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LDO2_ONSEL,
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LDO2_SLPSEL,
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LDO3_ONSEL,
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LDO3_SLPSEL,
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LDO4_ONSEL,
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LDO4_SLPSEL,
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LDO5_ONSEL,
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LDO5_SLPSEL,
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LDO6_ONSEL,
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LDO6_SLPSEL,
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LDO7_ONSEL,
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LDO7_SLPSEL,
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LDO8_ONSEL,
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LDO8_SLPSEL,
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};
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static struct rk808_reg ldo_initlist[] = {
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{LDO4_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_lcd*/
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{LDO5_ONSEL, LDOVSEL(1800, LDO_BASE18V)}, /*vcc18_codec*/
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{LDO6_ONSEL, LDOVSEL(1000, LDO_BASE08V)}, /*vcc10_lcd*/
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{LDO8_ONSEL, LDOVSEL(3300, LDO_BASE18V)}, /*vccio_sd*/
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};
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void pmic_init(unsigned int bus)
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{
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uint8_t read_reg;
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int i;
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for (i = 0; i < ARRAY_SIZE(ldo_initlist); i++) {
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struct rk808_reg *reg = &ldo_initlist[i];
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i2c_writeb(bus, RK808_ADDR, reg->reg, reg->val);
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}
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/*enable ldo4,ldo5,ldo6,ldo8*/
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i2c_readb(bus, RK808_ADDR, LDO_EN, &read_reg);
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i2c_writeb(bus, RK808_ADDR, LDO_EN, read_reg | LOD8EN | LOD6EN
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| LOD5EN | LOD4EN);
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}
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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||||||
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||||
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*
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* You should have received a copy of the GNU General Public License
|
||||||
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__
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#define __SOC_ROCKCHIP_RK3288_PMIC_H__
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void pmic_init(unsigned int bus);
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#endif
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@ -27,17 +27,34 @@
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#include <timestamp.h>
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#include <timestamp.h>
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#include <arch/cache.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/exception.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/rockchip/rk3288/sdram.h>
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#include <soc/rockchip/rk3288/sdram.h>
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||||||
|
#include <soc/rockchip/rk3288/clock.h>
|
||||||
|
#include "timer.h"
|
||||||
|
|
||||||
void main(void)
|
void main(void)
|
||||||
{
|
{
|
||||||
console_init();
|
#if CONFIG_COLLECT_TIMESTAMPS
|
||||||
|
uint64_t start_romstage_time;
|
||||||
|
uint64_t before_dram_time;
|
||||||
|
uint64_t after_dram_time;
|
||||||
|
uint64_t base_time = timestamp_get();
|
||||||
|
start_romstage_time = timestamp_get();
|
||||||
|
#endif
|
||||||
/* used for MMU and CBMEM setup, in MB */
|
/* used for MMU and CBMEM setup, in MB */
|
||||||
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
|
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
|
||||||
u32 dram_size = CONFIG_DRAM_SIZE_MB;
|
u32 dram_size = CONFIG_DRAM_SIZE_MB;
|
||||||
u32 dram_end = dram_start + dram_size;
|
u32 dram_end = dram_start + dram_size;
|
||||||
|
|
||||||
|
console_init();
|
||||||
|
|
||||||
|
#if CONFIG_COLLECT_TIMESTAMPS
|
||||||
|
before_dram_time = timestamp_get();
|
||||||
|
#endif
|
||||||
sdram_init(get_sdram_config());
|
sdram_init(get_sdram_config());
|
||||||
|
#if CONFIG_COLLECT_TIMESTAMPS
|
||||||
|
after_dram_time = timestamp_get();
|
||||||
|
#endif
|
||||||
mmu_init();
|
mmu_init();
|
||||||
/* Device memory below DRAM is uncached. */
|
/* Device memory below DRAM is uncached. */
|
||||||
mmu_config_range(0, dram_start, DCACHE_OFF);
|
mmu_config_range(0, dram_start, DCACHE_OFF);
|
||||||
|
@ -49,10 +66,18 @@ void main(void)
|
||||||
/* The space above DRAM is uncached. */
|
/* The space above DRAM is uncached. */
|
||||||
if (dram_end < 4096)
|
if (dram_end < 4096)
|
||||||
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
|
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
|
||||||
mmu_disable_range(0, 1);
|
|
||||||
dcache_mmu_enable();
|
dcache_mmu_enable();
|
||||||
|
|
||||||
|
setup_chromeos_gpios();
|
||||||
|
|
||||||
cbmem_initialize_empty();
|
cbmem_initialize_empty();
|
||||||
|
|
||||||
|
#if CONFIG_COLLECT_TIMESTAMPS
|
||||||
|
timestamp_init(base_time);
|
||||||
|
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
|
||||||
|
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
|
||||||
|
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
|
||||||
|
timestamp_add_now(TS_END_ROMSTAGE);
|
||||||
|
#endif
|
||||||
run_ramstage();
|
run_ramstage();
|
||||||
}
|
}
|
||||||
|
|
|
@ -21,14 +21,14 @@ IDBTOOL = util/rockchip/make_idb.py
|
||||||
|
|
||||||
#bootblock-y += bootblock.c
|
#bootblock-y += bootblock.c
|
||||||
bootblock-y += cbmem.c
|
bootblock-y += cbmem.c
|
||||||
bootblock-y += timer.c
|
|
||||||
bootblock-y += monotonic_timer.c
|
|
||||||
bootblock-y += media.c
|
|
||||||
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
|
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
|
||||||
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
|
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
|
||||||
endif
|
endif
|
||||||
|
bootblock-y += timer.c
|
||||||
|
bootblock-y += monotonic_timer.c
|
||||||
bootblock-y += clock.c
|
bootblock-y += clock.c
|
||||||
bootblock-y += spi.c
|
bootblock-y += spi.c
|
||||||
|
bootblock-y += media.c
|
||||||
|
|
||||||
romstage-y += cbmem.c
|
romstage-y += cbmem.c
|
||||||
romstage-y += timer.c
|
romstage-y += timer.c
|
||||||
|
|
|
@ -19,11 +19,9 @@
|
||||||
|
|
||||||
#include <stddef.h>
|
#include <stddef.h>
|
||||||
#include <cbmem.h>
|
#include <cbmem.h>
|
||||||
|
#include "soc.h"
|
||||||
#define FB_SIZE_MB 4
|
|
||||||
void *cbmem_top(void)
|
void *cbmem_top(void)
|
||||||
{
|
{
|
||||||
return (void *)(CONFIG_SYS_SDRAM_BASE +
|
return (void *)(get_fb_base_kb()*KiB);
|
||||||
(CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -339,3 +339,34 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
|
||||||
printk(BIOS_ERR, "do not support this spi bus\n");
|
printk(BIOS_ERR, "do not support this spi bus\n");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static u32 clk_gcd(u32 a, u32 b)
|
||||||
|
{
|
||||||
|
while (b != 0) {
|
||||||
|
int r = b;
|
||||||
|
b = a % b;
|
||||||
|
a = r;
|
||||||
|
}
|
||||||
|
return a;
|
||||||
|
}
|
||||||
|
|
||||||
|
void rkclk_configure_i2s(unsigned int hz)
|
||||||
|
{
|
||||||
|
int n, d;
|
||||||
|
int v;
|
||||||
|
|
||||||
|
/* i2s source clock: gpll
|
||||||
|
i2s0_outclk_sel: clk_i2s
|
||||||
|
i2s0_clk_sel: divider ouput from fraction
|
||||||
|
i2s0_pll_div_con: 0*/
|
||||||
|
writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 ,
|
||||||
|
1 << 15 | 0 << 12 | 1 << 8 | 0 << 0),
|
||||||
|
&cru_ptr->cru_clksel_con[4]);
|
||||||
|
|
||||||
|
/* set frac divider */
|
||||||
|
v = clk_gcd(GPLL_HZ, hz);
|
||||||
|
n = (GPLL_HZ / v) & (0xffff);
|
||||||
|
d = (hz / v) & (0xffff);
|
||||||
|
assert(hz == GPLL_HZ / n * d);
|
||||||
|
writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]);
|
||||||
|
}
|
||||||
|
|
|
@ -31,5 +31,6 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
|
||||||
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
|
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
|
||||||
void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
|
void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
|
||||||
void rkclk_configure_ddr(unsigned int hz);
|
void rkclk_configure_ddr(unsigned int hz);
|
||||||
|
void rkclk_configure_i2s(unsigned int hz);
|
||||||
|
|
||||||
#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */
|
#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */
|
||||||
|
|
|
@ -17,8 +17,8 @@
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ROCKCHIP_RK3288_TIMER_H__
|
#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__
|
||||||
#define __ROCKCHIP_RK3288_TIMER_H__
|
#define __SOC_ROCKCHIP_RK3288_TIMER_H__
|
||||||
|
|
||||||
#include "addressmap.h"
|
#include "addressmap.h"
|
||||||
|
|
||||||
|
@ -40,4 +40,4 @@ static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
|
||||||
|
|
||||||
void rk3288_init_timer(void);
|
void rk3288_init_timer(void);
|
||||||
|
|
||||||
#endif /* __ROCKCHIP_RK3288_TIMER_H__ */
|
#endif /* __SOC_ROCKCHIP_RK3288_TIMER_H__ */
|
||||||
|
|
|
@ -24,6 +24,9 @@
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <bootmode.h>
|
#include <bootmode.h>
|
||||||
|
|
||||||
|
/*for mainboard use only*/
|
||||||
|
void setup_chromeos_gpios(void);
|
||||||
|
|
||||||
/* functions implemented in vbnv.c: */
|
/* functions implemented in vbnv.c: */
|
||||||
int get_recovery_mode_from_vbnv(void);
|
int get_recovery_mode_from_vbnv(void);
|
||||||
int vboot_wants_oprom(void);
|
int vboot_wants_oprom(void);
|
||||||
|
|
Loading…
Reference in New Issue