mb/google/brya/var/felwinter: adjust I2C5 times for TP

This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5.

BUG=b:249031186
BRANCH=brya
TEST=TP function is normal from EE check.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5e756b7d7e14cace24ef2dfbb323c840c867ae1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>

src/mainboard/google/brya/variants/felwinter/overridetree.cb

@@ -83,7 +83,12 @@ chip soc/intel/alderlake
 			.speed = I2C_SPEED_FAST,
 			.rise_time_ns = 550,
 			.fall_time_ns = 400,
-			.data_hold_time_ns = 50,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 160,
+				.scl_hcnt = 70,
+				.sda_hold = 40,
+			}
 		},
 	}"