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nb/intel/haswell: Add `mb_late_romstage_setup` function 

This function is called at the end of `romstage_common`. Only one board
makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call
it after `romstage_common` has done nearly everything.

Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-03 12:29:03 +02:00
parent c06648b8c1
commit 73fa035b20
3 changed files with 27 additions and 17 deletions
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37
src/mainboard/lenovo/t440p/romstage.c
View File

@ -23,6 +23,26 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
} }
void mb_late_romstage_setup(void)
{
u8 enable_peg;
if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS)
enable_peg = 0;
bool power_en = pmh7_dgpu_power_state();
if (enable_peg != power_en)
pmh7_dgpu_power_enable(!power_en);
if (!enable_peg) {
// Hide disabled dGPU device
u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
reg32 &= ~DEVEN_D1F0EN;
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
}
void mainboard_romstage_entry(void) void mainboard_romstage_entry(void)
{ {
struct pei_data pei_data = { struct pei_data pei_data = {
@ -77,21 +97,4 @@ void mainboard_romstage_entry(void)
}; };
romstage_common(&romstage_params); romstage_common(&romstage_params);
u8 enable_peg;
if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS)
enable_peg = 0;
bool power_en = pmh7_dgpu_power_state();
if (enable_peg != power_en)
pmh7_dgpu_power_enable(!power_en);
if (!enable_peg) {
// Hide disabled dGPU device
u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
reg32 &= ~DEVEN_D1F0EN;
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
} }

1
src/northbridge/intel/haswell/haswell.h
View File

@ -195,6 +195,7 @@ struct romstage_params {
void (*copy_spd)(struct pei_data *peid); void (*copy_spd)(struct pei_data *peid);
}; };
void romstage_common(const struct romstage_params *params); void romstage_common(const struct romstage_params *params);
void mb_late_romstage_setup(void); /* optional */
void haswell_early_initialization(void); void haswell_early_initialization(void);
void haswell_late_initialization(void); void haswell_late_initialization(void);

6
src/northbridge/intel/haswell/romstage.c
View File

@ -13,6 +13,10 @@
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/me.h>
void __weak mb_late_romstage_setup(void)
{
}
void romstage_common(const struct romstage_params *params) void romstage_common(const struct romstage_params *params)
{ {
int wake_from_s3; int wake_from_s3;
@ -77,5 +81,7 @@ void romstage_common(const struct romstage_params *params)
romstage_handoff_init(wake_from_s3); romstage_handoff_init(wake_from_s3);
mb_late_romstage_setup();
post_code(0x3f); post_code(0x3f);
} }