intel/sandybridge: Don't hardcode platform type

* Add a function to return CPU platform ID bits
* Add a function to return platform type
** Platform id is 4 on Lenovo T430 (mobile)
** Platform id is 1 on HP8200 (desktop)
* Use introduced method to handle platform specific code
* Use enum for platform type
* Report platform ID

Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/cpu/intel/model_206ax/Makefile.inc

@@ -5,6 +5,10 @@ subdirs-y += ../common
 
 ramstage-y += acpi.c
 
+ramstage-y += common.c
+romstage-y += common.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c

src/cpu/intel/model_206ax/common.c

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+#define IA32_PLATFORM_ID		0x17
+
+int get_platform_id(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_PLATFORM_ID);
+	/* Read Platform Id Bits 52:50 */
+	return (msr.hi >> 18) & 0x7;
+}

src/cpu/intel/model_206ax/model_206ax.h

@@ -123,5 +123,6 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 void smm_relocate(void);
 #endif
+int get_platform_id(void);
 
 #endif

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -514,6 +514,9 @@ static void model_206ax_init(struct device *cpu)
 	fill_processor_name(processor_name);
 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
+	/* Print platform ID */
+	printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id());
+
 	/* Setup MTRRs based on physical address size */
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();

src/northbridge/intel/sandybridge/Makefile.inc

@@ -25,6 +25,11 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
 ramstage-y += acpi.c
 
 romstage-y += ram_calc.c
+
+ramstage-y += common.c
+romstage-y += common.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+
 ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
 romstage-y += raminit.c
 romstage-y += raminit_common.c

src/northbridge/intel/sandybridge/common.c

@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "sandybridge.h"
+
+enum platform_type get_platform_type(void)
+{
+	const int id = get_platform_id();
+	if (id != 1 && id != 4)
+		printk(BIOS_WARNING, "WARN: Unknown platform id 0x%x\n", id);
+
+	return (id == 4) ? PLATFORM_MOBILE : PLATFORM_DESKTOP_SERVER;
+}

src/northbridge/intel/sandybridge/early_init.c

@@ -186,7 +186,7 @@ static void start_peg_link_training(void)
 	}
 }
 
-void sandybridge_early_initialization(int chipset_type)
+void sandybridge_early_initialization(void)
 {
 	u32 capid0_a;
 	u32 deven;
@@ -195,10 +195,12 @@ void sandybridge_early_initialization(int chipset_type)
 	/* Device ID Override Enable should be done very early */
 	capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
 	if (capid0_a & (1 << 10)) {
+		const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
+
 		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
 		reg8 &= ~7; /* Clear 2:0 */
 
-		if (chipset_type == SANDYBRIDGE_MOBILE)
+		if (is_mobile)
 			reg8 |= 1; /* Set bit 0 */
 
 		pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);

src/northbridge/intel/sandybridge/raminit.c

@@ -308,7 +308,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
 		return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);
 }
 
-static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
+static void init_dram_ddr3(int min_tck, int s3resume)
 {
 	int me_uma_size;
 	int cbmem_was_inited;
@@ -398,7 +398,6 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
 	if (!fast_boot) {
 		/* Reset internal state */
 		memset(&ctrl, 0, sizeof(ctrl));
-		ctrl.mobile = mobile;
 		ctrl.tCK = min_tck;
 
 		/* Get architecture */
@@ -421,7 +420,6 @@ static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
 
 		/* Reset internal state */
 		memset(&ctrl, 0, sizeof(ctrl));
-		ctrl.mobile = mobile;
 		ctrl.tCK = min_tck;
 
 		/* Get architecture */
@@ -480,5 +478,5 @@ void perform_raminit(int s3resume)
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
 
-	init_dram_ddr3(1, get_mem_min_tck(), s3resume);
+	init_dram_ddr3(get_mem_min_tck(), s3resume);
 }

src/northbridge/intel/sandybridge/raminit_common.c

@@ -763,6 +763,7 @@ static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
 {
 	u16 mr0reg, mch_cas, mch_wr;
 	static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 };
+	const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
 
 	/* DLL Reset - self clearing - set after CLK frequency has been changed */
 	mr0reg = 0x100;
@@ -783,7 +784,7 @@ static u32 make_mr0(ramctr_timing * ctrl, u8 rank)
 	mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9);
 
 	// Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature
-	mr0reg = (mr0reg & ~0x1000) | (!ctrl->mobile << 12);
+	mr0reg = (mr0reg & ~0x1000) | (!is_mobile << 12);
 	return mr0reg;
 }
 
@@ -3193,6 +3194,8 @@ static int encode_5d10(int ns)
 /* FIXME: values in this function should be hardware revision-dependent.  */
 void final_registers(ramctr_timing * ctrl)
 {
+	const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
+
 	int channel;
 	int t1_cycles = 0, t1_ns = 0, t2_ns;
 	int t3_ns;
@@ -3203,7 +3206,7 @@ void final_registers(ramctr_timing * ctrl)
 	write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000);	// OK
 	write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000);	// OK
 
-	if (ctrl->mobile)
+	if (is_mobile)
 		/* APD - DLL Off, 64 DCLKs until idle, decision per rank */
 		MCHBAR32(PM_PDWN_Config) = 0x00000740;
 	else

src/northbridge/intel/sandybridge/raminit_common.h

@@ -75,7 +75,6 @@ struct ramctr_timing_st;
 
 typedef struct ramctr_timing_st {
 	u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
-	int mobile;
 	int sandybridge;
 
 	/* DDR base_freq = 100 Mhz / 133 Mhz */

src/northbridge/intel/sandybridge/romstage.c

@@ -85,7 +85,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
-	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	sandybridge_early_initialization();
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
 	s3resume = southbridge_detect_s3_resume();

src/northbridge/intel/sandybridge/sandybridge.h

@@ -17,11 +17,6 @@
 #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
 #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
 
-/* Chipset types */
-#define SANDYBRIDGE_MOBILE	0
-#define SANDYBRIDGE_DESKTOP	1
-#define SANDYBRIDGE_SERVER	2
-
 /* Device ID for SandyBridge and IvyBridge */
 #define BASE_REV_SNB	0x00
 #define BASE_REV_IVB	0x50
@@ -62,6 +57,13 @@
 
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Chipset types */
+enum platform_type {
+	PLATFORM_MOBILE = 0,
+	PLATFORM_DESKTOP_SERVER,
+};
 
 #include <rules.h>
 
@@ -204,7 +206,7 @@ static inline void barrier(void) { asm("" ::: "memory"); }
 void intel_sandybridge_finalize_smm(void);
 #else /* !__SMM__ */
 int bridge_silicon_revision(void);
-void sandybridge_early_initialization(int chipset_type);
+void sandybridge_early_initialization(void);
 void sandybridge_init_iommu(void);
 void sandybridge_late_initialization(void);
 void northbridge_romstage_finalize(int s3resume);
@@ -224,6 +226,7 @@ void mainboard_early_init(int s3resume);
 void mainboard_config_superio(void);
 int mainboard_should_reset_usb(int s3resume);
 void perform_raminit(int s3resume);
+enum platform_type get_platform_type(void);
 
 #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>