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mb/siemens/mc_ehl1: Disable power management features for SATA 

Features like DevSLP and Aggressive Link Power Management are not
supported on this mainboard and are therefore disabled.

Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Werner Zeh 2021-07-21 07:26:38 +02:00 committed by Patrick Georgi
parent b90aba43c1
commit 75178071fb
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -64,11 +64,11 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[5]" = "0xFF" register "PcieClkSrcClkReq[5]" = "0xFF"
# Storage (SATA/SDCARD/EMMC) related UPDs # Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "1" register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[1]" = "0"
register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcDdr50Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1"