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mb/google/hatch: Enable S0ix 

BUG=b:123540469
BRANCH=None
TEST=None

Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31157
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2019-01-29 15:30:14 -08:00
parent fb7a1a420c
commit 757571eec1
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -55,6 +55,8 @@ chip soc/intel/cannonlake
register "HeciEnabled" = "1"
# Enable Speed Shift Technology support
register "speed_shift_enable" = "1"
# Enable S0ix
register "s0ix_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1