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palkia: separate the gpio pins control for the second touch 

There are two touch screen controllers on the Palkia device.
One is on the lid; another is on the base. To support
the different control path (for example: turning off the base's
touch event when we don't want to use it however still keeping
the lid's touch event), we use the different gpio pins to control
the second touch. As a result, we need to modify the devicetree
to adopt this change. With this change, we can control the
primary and secondary touch screen controller respectively.

BUG=b:149714955
TEST=lid/base touch screen works correctly

Change-Id: I1f896e334e51c78300af724cbef8d57641ae5612
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Zhuohao Lee 2020-06-08 15:37:23 +08:00 committed by Furquan Shaikh
parent 4229dfc215
commit 7587526583
2 changed files with 6 additions and 2 deletions
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4
src/mainboard/google/hatch/variants/palkia/gpio.c
View File

@ -45,6 +45,10 @@ static const struct pad_config gpio_table[] = {
/* C23 : UART2_CTS# ==> NC */
PAD_NC(GPP_C23, NONE),
/* D4 : USI_BASE_REPORT_EN */
PAD_CFG_GPO(GPP_D4, 0, DEEP),
/* D10 : GPP_D10 ==> EN_PP3300_DX_BASE_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D10, 0, DEEP),
/* D16 : USI_INT_L */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),

4
src/mainboard/google/hatch/variants/palkia/overridetree.cb
View File

@ -136,12 +136,12 @@ chip soc/intel/cannonlake
"ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)"
register "generic.probed" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D10)"
register "generic.enable_delay_ms" = "12"
register "generic.enable_off_delay_ms" = "10"
register "generic.has_power_resource" = "1"
register "generic.stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
register "generic.stop_delay_ms" = "15"
register "generic.stop_off_delay_ms" = "5"
register "hid_desc_reg_offset" = "0x01"