sb/intel/i82801jx: Rename GNVS `PSVT` and `CRTT`
Most other Intel southbridges call those `TPSV` and `TCRT` instead. Change-Id: Id4c30cd53abc544b743eb80696bfafe45929208e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42644 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -36,11 +36,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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/* Thermal policy */
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Offset (0x14),
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ACTT, 8, // 0x14 - active trip point
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PSVT, 8, // 0x15 - passive trip point
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TPSV, 8, // 0x15 - passive trip point
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TC1V, 8, // 0x16 - passive trip point TC1
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TC2V, 8, // 0x17 - passive trip point TC2
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TSPV, 8, // 0x18 - passive trip point TSP
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CRTT, 8, // 0x19 - critical trip point
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TCRT, 8, // 0x19 - critical trip point
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DTSE, 8, // 0x1a - Digital Thermal Sensor enable
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DTS1, 8, // 0x1b - DT sensor 1
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FLVL, 8, // 0x1c - current fan level
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@ -22,11 +22,11 @@ typedef struct {
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u8 dckn; /* 0x13 - PCIe docking state */
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/* Thermal policy */
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u8 actt; /* 0x14 - active trip point */
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u8 psvt; /* 0x15 - passive trip point */
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u8 tpsv; /* 0x15 - passive trip point */
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u8 tc1v; /* 0x16 - passive trip point TC1 */
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u8 tc2v; /* 0x17 - passive trip point TC2 */
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u8 tspv; /* 0x18 - passive trip point TSP */
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u8 crtt; /* 0x19 - critical trip point */
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u8 tcrt; /* 0x19 - critical trip point */
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u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
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u8 dts1; /* 0x1b - DT sensor 1 */
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u8 flvl; /* 0x1c - current fan level */
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