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mb/google/zork: Configure EMMC_RESET_L to drive high 

Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC
specification for eMMC, RST_n_FUNCTION defaults to temporarily disable
reset using RST_n signal (which is connected to EMMC_RESET_L on
zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making
the reset signal unused. The spec also says that there are no internal
pulls on the card and hence the RST_n signal should be driven
appropriately to prevent the input circuits from flowing unnecessary
leakage current.

Thus, even though the line remains unused, since it is connected in
hardware, this change drives EMMC_RESET_L to high.

BUG=b:169222156
BRANCH=zork
TEST=emerge-zork coreboot
     eMMC DUT reboot/suspend x100 iterations pass

Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kevin Chiu 2020-09-26 20:34:28 +08:00 committed by Furquan Shaikh
parent bbbdba1e50
commit 768f59a32f
2 changed files with 4 additions and 4 deletions
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4
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -79,8 +79,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
* access will be very slow.
*/
PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
/* EMMC_RESET */
PAD_GPO(GPIO_68, LOW),
/* EMMC_RESET_L */
PAD_GPO(GPIO_68, HIGH),
/* RAM ID 3 */
PAD_GPI(GPIO_69, PULL_NONE),
/* EMMC_CLK */

4
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -85,8 +85,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
* access will be very slow.
*/
PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
/* EMMC_RESET */
PAD_GPO(GPIO_68, LOW),
/* EMMC_RESET_L */
PAD_GPO(GPIO_68, HIGH),
/* FPMCU_BOOT0 - TODO: Check this */
PAD_GPO(GPIO_69, LOW),
/* EMMC_CLK */