Add the AMD Torpedo mainboard

The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.

Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/amd/Kconfig

@@ -29,6 +29,8 @@ config BOARD_AMD_INAGUA
 	bool "Inagua"
 config BOARD_AMD_PERSIMMON
 	bool "Persimmon"
+config BOARD_AMD_TORPEDO
+	bool "Torpedo"
 endchoice
 
 source "src/mainboard/amd/db800/Kconfig"
@@ -44,6 +46,7 @@ source "src/mainboard/amd/tilapia_fam10/Kconfig"
 source "src/mainboard/amd/bimini_fam10/Kconfig"
 source "src/mainboard/amd/inagua/Kconfig"
 source "src/mainboard/amd/persimmon/Kconfig"
+source "src/mainboard/amd/torpedo/Kconfig"
 
 config MAINBOARD_VENDOR
 	string

src/mainboard/amd/torpedo/BiosCallOuts.c

@@ -0,0 +1,670 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "Hudson-2.h"
+
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01   1
+#endif
+
+#ifndef SB_GPIO_REG24
+#define SB_GPIO_REG24   24
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27   27
+#endif
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+  {AGESA_ALLOCATE_BUFFER,
+   BiosAllocateBuffer
+  },
+
+  {AGESA_DEALLOCATE_BUFFER,
+   BiosDeallocateBuffer
+  },
+
+  {AGESA_DO_RESET,
+   BiosReset
+  },
+
+  {AGESA_LOCATE_BUFFER,
+   BiosLocateBuffer
+  },
+
+  {AGESA_READ_SPD,
+   BiosReadSpd
+  },
+
+  {AGESA_READ_SPD_RECOVERY,
+   BiosDefaultRet
+  },
+
+  {AGESA_RUNFUNC_ONAP,
+   BiosRunFuncOnAp
+  },
+
+  {AGESA_GNB_PCIE_SLOT_RESET,
+   BiosGnbPcieSlotReset
+  },
+
+  {AGESA_GET_IDS_INIT_DATA,
+   BiosGetIdsInitData
+  },
+
+  {AGESA_HOOKBEFORE_DRAM_INIT,
+   BiosHookBeforeDramInit
+  },
+
+  {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+   BiosHookBeforeDramInitRecovery
+  },
+
+  {AGESA_HOOKBEFORE_DQS_TRAINING,
+   BiosHookBeforeDQSTraining
+  },
+
+  {AGESA_HOOKBEFORE_EXIT_SELF_REF,
+   BiosHookBeforeExitSelfRefresh
+  },
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINTN i;
+  AGESA_STATUS CalloutStatus;
+  UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+  for (i = 0; i < CallOutCount; i++)
+  {
+    if (BiosCallouts[i].CalloutName == Func)
+    {
+      break;
+    }
+  }
+
+  if(i >= CallOutCount)
+  {
+    return AGESA_UNSUPPORTED;
+  }
+
+  CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+  return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+  /*{
+    AGESA_IDS_NV_MAIN_PLL_CON,
+    0x1
+  },
+  {
+    AGESA_IDS_NV_MAIN_PLL_FID_EN,
+    0x1
+  },
+  {
+    AGESA_IDS_NV_MAIN_PLL_FID,
+    0x8
+  },
+
+  {
+    AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+  },
+  {
+    AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+  },
+  {
+    AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+  },
+  {
+    AGESA_IDS_NV_FORCE_NB_PSTATE,
+  },
+*/
+  {
+    0xFFFF,
+    0xFFFF
+  }
+};
+
+#define   NUM_IDS_ENTRIES    (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINTN   i;
+  IDS_NV_ITEM *IdsPtr;
+
+  IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+  if (Data == IDS_CALLOUT_INIT) {
+    for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+      IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+      IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINT32              AvailableHeapSize;
+  UINT8               *BiosHeapBaseAddr;
+  UINT32              CurrNodeOffset;
+  UINT32              PrevNodeOffset;
+  UINT32              FreedNodeOffset;
+  UINT32              BestFitNodeOffset;
+  UINT32              BestFitPrevNodeOffset;
+  UINT32              NextFreeOffset;
+  BIOS_BUFFER_NODE   *CurrNodePtr;
+  BIOS_BUFFER_NODE   *FreedNodePtr;
+  BIOS_BUFFER_NODE   *BestFitNodePtr;
+  BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+  BIOS_BUFFER_NODE   *NextFreePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+  AllocParams->BufferPointer = NULL;
+
+  AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+    /* First allocation */
+    CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+    CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+    CurrNodePtr->BufferSize = AllocParams->BufferLength;
+    CurrNodePtr->NextNodeOffset = 0;
+    AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+    /* Update the remaining free space */
+    FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+    FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+    FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+    FreedNodePtr->NextNodeOffset = 0;
+
+    /* Update the offsets for Allocated and Freed nodes */
+    BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+    BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+  } else {
+    /* Find out whether BufferHandle has been allocated on the heap. */
+    /* If it has, return AGESA_BOUNDS_CHK */
+    CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+    while (CurrNodeOffset != 0) {
+      CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+      if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+        return AGESA_BOUNDS_CHK;
+      }
+      CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+      /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+       to the end of the allocated nodes list.
+      */
+
+    }
+    /* Find the node that best fits the requested buffer size */
+    FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+    PrevNodeOffset = FreedNodeOffset;
+    BestFitNodeOffset = 0;
+    BestFitPrevNodeOffset = 0;
+    while (FreedNodeOffset != 0) {
+      FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+      if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+        if (BestFitNodeOffset == 0) {
+          /* First node that fits the requested buffer size */
+          BestFitNodeOffset = FreedNodeOffset;
+          BestFitPrevNodeOffset = PrevNodeOffset;
+        } else {
+          /* Find out whether current node is a better fit than the previous nodes */
+          BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+          if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+            BestFitNodeOffset = FreedNodeOffset;
+            BestFitPrevNodeOffset = PrevNodeOffset;
+          }
+        }
+      }
+      PrevNodeOffset = FreedNodeOffset;
+      FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+    } /* end of while loop */
+
+
+    if (BestFitNodeOffset == 0) {
+      /* If we could not find a node that fits the requested buffer */
+      /* size, return AGESA_BOUNDS_CHK */
+      return AGESA_BOUNDS_CHK;
+    } else {
+      BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+      BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+      /* If BestFitNode is larger than the requested buffer, fragment the node further */
+      if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+        NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+        NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+        NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+        NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+      } else {
+        /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+        NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+      }
+
+      /* If BestFitNode is the first buffer in the list, then update
+         StartOfFreedNodes to reflect the new free node
+      */
+      if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+        BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+      } else {
+        BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+      }
+
+      /* Add BestFitNode to the list of Allocated nodes */
+      CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+      BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+      BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+      BestFitNodePtr->NextNodeOffset = 0;
+
+      /* Remove BestFitNode from list of Freed nodes */
+      AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+  UINT8               *BiosHeapBaseAddr;
+  UINT32              AllocNodeOffset;
+  UINT32              PrevNodeOffset;
+  UINT32              NextNodeOffset;
+  UINT32              FreedNodeOffset;
+  UINT32              EndNodeOffset;
+  BIOS_BUFFER_NODE   *AllocNodePtr;
+  BIOS_BUFFER_NODE   *PrevNodePtr;
+  BIOS_BUFFER_NODE   *FreedNodePtr;
+  BIOS_BUFFER_NODE   *NextNodePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+  /* Find target node to deallocate in list of allocated nodes.
+     Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+  */
+  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+  PrevNodeOffset = AllocNodeOffset;
+
+  while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+    if (AllocNodePtr->NextNodeOffset == 0) {
+      return AGESA_BOUNDS_CHK;
+    }
+    PrevNodeOffset = AllocNodeOffset;
+    AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+    AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+  }
+
+  /* Remove target node from list of allocated nodes */
+  PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+  PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+  /* Zero out the buffer, and clear the BufferHandle */
+  LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+  AllocNodePtr->BufferHandle = 0;
+  AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+  /* Add deallocated node in order to the list of freed nodes */
+  FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+  FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+  EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+  if (AllocNodeOffset < FreedNodeOffset) {
+    /* Add to the start of the freed list */
+    if (EndNodeOffset == FreedNodeOffset) {
+      /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+      AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+      AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+      /* Clear the BufferSize and NextNodeOffset of the previous first node */
+      FreedNodePtr->BufferSize = 0;
+      FreedNodePtr->NextNodeOffset = 0;
+
+    } else {
+      /* Otherwise, add freed node to the start of the list
+         Update NextNodeOffset and BufferSize to include the
+         size of BIOS_BUFFER_NODE
+      */
+      AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+    }
+    /* Update StartOfFreedNodes to the new first node */
+    BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+  } else {
+    /* Traverse list of freed nodes to find where the deallocated node
+       should be place
+    */
+    NextNodeOffset = FreedNodeOffset;
+    NextNodePtr = FreedNodePtr;
+    while (AllocNodeOffset > NextNodeOffset) {
+      PrevNodeOffset = NextNodeOffset;
+      if (NextNodePtr->NextNodeOffset == 0) {
+        break;
+      }
+      NextNodeOffset = NextNodePtr->NextNodeOffset;
+      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+    }
+
+    /* If deallocated node is adjacent to the next node,
+       concatenate both nodes
+    */
+    if (NextNodeOffset == EndNodeOffset) {
+      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+      AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+      AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+      NextNodePtr->BufferSize = 0;
+      NextNodePtr->NextNodeOffset = 0;
+    } else {
+      /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+      AllocNodePtr->NextNodeOffset = NextNodeOffset;
+    }
+    /* If deallocated node is adjacent to the previous node,
+       concatenate both nodes
+    */
+    PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+    EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+    if (AllocNodeOffset == EndNodeOffset) {
+      PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+      PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+      AllocNodePtr->BufferSize = 0;
+      AllocNodePtr->NextNodeOffset = 0;
+    } else {
+      PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  UINT32              AllocNodeOffset;
+  UINT8               *BiosHeapBaseAddr;
+  BIOS_BUFFER_NODE   *AllocNodePtr;
+  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+  AGESA_BUFFER_PARAMS *AllocParams;
+
+  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+  while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+    if (AllocNodePtr->NextNodeOffset == 0) {
+      AllocParams->BufferPointer = NULL;
+      AllocParams->BufferLength = 0;
+      return AGESA_BOUNDS_CHK;
+    } else {
+      AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+      AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+    }
+  }
+
+  AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+  AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+  return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS        Status;
+
+  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+  return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS        Status;
+  UINT8                 Value;
+  UINTN               ResetType;
+  AMD_CONFIG_PARAMS   *StdHeader;
+
+  ResetType = Data;
+  StdHeader = ConfigPtr;
+
+  //
+  // Perform the RESET based upon the ResetType. In case of
+  // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+  // AmdResetManager. During the critical condition, where reset is required
+  // immediately, the reset will be invoked directly by writing 0x04 to port
+  // 0xCF9 (Reset Port).
+  //
+  switch (ResetType) {
+  case WARM_RESET_WHENEVER:
+  case COLD_RESET_WHENEVER:
+    break;
+
+  case WARM_RESET_IMMEDIATELY:
+  case COLD_RESET_IMMEDIATELY:
+      Value = 0x06;
+      LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+    break;
+
+  default:
+    break;
+  }
+
+  Status = 0;
+  return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS Status;
+  Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
+
+  return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_UNSUPPORTED;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_SUCCESS;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS      Status;
+  UINTN             FcnData;
+  MEM_DATA_STRUCT   *MemData;
+  UINT32            AcpiMmioAddr;
+  UINT32            GpioMmioAddr;
+  UINT8             Data8;
+  UINT16            Data16;
+  UINT8             TempData8;
+
+  FcnData = Data;
+  MemData = ConfigPtr;
+
+  Status  = AGESA_SUCCESS;
+  /* Get SB MMIO Base (AcpiMmioAddr) */
+  WriteIo8 (0xCD6, 0x27);
+  Data8   = ReadIo8(0xCD7);
+  Data16  = Data8<<8;
+  WriteIo8 (0xCD6, 0x26);
+  Data8   = ReadIo8(0xCD7);
+  Data16  |= Data8;
+  AcpiMmioAddr = (UINT32)Data16 << 16;
+  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+  if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_5) {
+  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+    Data8 |= BIT6;
+    Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+  } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_35) {
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+    Data8 |= BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+  } else if(MemData->ParameterListPtr->DDR3Voltage == VOLT1_25) {
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+  } else {}
+  return Status;
+}
+
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_SUCCESS;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  return AGESA_SUCCESS;
+}
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+  AGESA_STATUS Status;
+  UINTN                 FcnData;
+  PCIe_SLOT_RESET_INFO  *ResetInfo;
+
+  UINT32  GpioMmioAddr;
+  UINT32  AcpiMmioAddr;
+  UINT8   Data8;
+  UINT16  Data16;
+
+  FcnData   = Data;
+  ResetInfo = ConfigPtr;
+  // Get SB MMIO Base (AcpiMmioAddr)
+  WriteIo8(0xCD6, 0x27);
+  Data8 = ReadIo8(0xCD7);
+  Data16=Data8<<8;
+  WriteIo8(0xCD6, 0x26);
+  Data8 = ReadIo8(0xCD7);
+  Data16|=Data8;
+  AcpiMmioAddr = (UINT32)Data16 << 16;
+  Status = AGESA_UNSUPPORTED;
+  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+
+  if (ResetInfo->ResetControl == DeassertSlotReset) {
+    if (ResetInfo->ResetId & BIT2+BIT3) {    //de-assert
+      // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+      Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
+      if (Data8 & BIT7) {
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+        while (!(Data8 & BIT7)) {
+          Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
+        } 						
+        // GPIO44: PE_GPIO0 MXM Reset
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+        Data8 |= BIT6 ;
+        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+        Status = AGESA_SUCCESS;
+      }
+    } else {
+      Status = AGESA_UNSUPPORTED;
+    }
+    // Travis
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+    Data8 |= BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+    //DE-Assert ALL PCIE RESET
+    // APU GPP0 (Dev 4)
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+        Data8 |= BIT6 ;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+    // APU GPP1 (Dev 5)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+    Data8 |= BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+    // APU GPP2 (Dev 6)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+    Data8 |= BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+    // APU GPP3 (Dev 7)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+    Data8 |= BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+  } else {
+    if (ResetInfo->ResetId & (BIT2+BIT3)) {  //Pcie Slot Reset is supported
+      // GPIO44: PE_GPIO0 MXM Reset
+      Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
+      Data8 &= ~(UINT8)BIT6;
+      Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
+        Status = AGESA_SUCCESS;
+      }
+    // Travis
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
+        Data8 &= ~(UINT8)BIT6 ;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
+    //Assert ALL PCIE RESET
+    // APU GPP0 (Dev 4)
+        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+    Data8 &= ~(UINT8)BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
+    // APU GPP1 (Dev 5)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
+    Data8 &= ~(UINT8)BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
+    // APU GPP2 (Dev 6)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
+    Data8 &= ~(UINT8)BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
+    // APU GPP3 (Dev 7)
+    Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
+    Data8 &= ~(UINT8)BIT6;
+    Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
+  }
+  return  Status;
+}

src/mainboard/amd/torpedo/BiosCallOuts.h

@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define BIOS_HEAP_START_ADDRESS  0x00010000
+#define BIOS_HEAP_SIZE       0x20000   /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+  //UINT32 AvailableSize;
+  UINT32 StartOfAllocatedNodes;
+  UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+  UINT32 BufferHandle;
+  UINT32 BufferSize;
+  UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32  Func,UINT32  Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+// These registers are not defined in cimx/SB900/Hudson-2.h
+#define SB_GPIO_REG02   2
+#define SB_GPIO_REG15   15
+#define SB_GPIO_REG25   25
+#endif //_BIOS_CALLOUT_H_

src/mainboard/amd/torpedo/Kconfig

@@ -0,0 +1,222 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+if BOARD_AMD_TORPEDO
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+        def_bool y
+  select ARCH_X86
+        select DIMM_DDR3
+        select DIMM_UNREGISTERED
+  select CPU_AMD_AGESA_FAMILY12
+  select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
+  select NORTHBRIDGE_AMD_AGESA_FAMILY12
+  select SOUTHBRIDGE_AMD_CIMX_SB900
+  select SUPERIO_SMSC_KBC1100
+  select BOARD_HAS_FADT
+        select HAVE_BUS_CONFIG
+        select HAVE_OPTION_TABLE
+        select HAVE_PIRQ_TABLE
+        select HAVE_MP_TABLE
+        select HAVE_MAINBOARD_RESOURCES
+        select HAVE_HARD_RESET
+        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+        select LIFT_BSP_APIC_ID
+  select SERIAL_CPU_INIT
+  select AMDMCT
+        select HAVE_ACPI_TABLES
+  select BOARD_ROMSIZE_KB_2048
+  select ENABLE_APIC_EXT_ID
+  select TINY_BOOTBLOCK
+        select GFXUMA
+
+config AMD_AGESA
+        bool
+        default y
+
+config AMD_CIMX_SB900
+        bool
+        default y
+
+config MAINBOARD_DIR
+        string
+        default amd/torpedo
+
+config APIC_ID_OFFSET
+        hex
+        default 0x0
+
+config MAINBOARD_PART_NUMBER
+        string
+        default "Torpedo"
+
+config HW_MEM_HOLE_SIZEK
+        hex
+        default 0x200000
+
+config MAX_CPUS
+        int
+        default 4
+
+config MAX_PHYSICAL_CPUS
+        int
+        default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+        bool
+        default n
+
+config MEM_TRAIN_SEQ
+        int
+        default 2
+
+config SB_HT_CHAIN_ON_BUS0
+        int
+        default 1
+
+config HT_CHAIN_END_UNITID_BASE
+        hex
+        default 0x1
+
+config HT_CHAIN_UNITID_BASE
+        hex
+        default 0x0
+
+config IRQ_SLOT_COUNT
+        int
+        default 11
+
+config RAMTOP
+        hex
+        default 0x1000000
+
+config HEAP_SIZE
+        hex
+        default 0xc0000
+
+config STACK_SIZE
+        hex
+        default 0x10000
+
+config ACPI_SSDTX_NUM
+        int
+        default 0
+
+config RAMBASE
+        hex
+        default 0x200000
+
+config SIO_PORT
+        hex
+        default 0x2e
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default y
+
+config WARNINGS_ARE_ERRORS
+	bool
+	default n
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config VGA_BIOS
+	bool
+	default n
+
+#config VGA_BIOS_FILE
+#	string "VGA BIOS path and filename"
+#	depends on VGA_BIOS
+#	default "rom/video/LlanoGenericVbios.bin"
+
+config VGA_BIOS_ID
+	string "VGA device PCI IDs"
+	depends on VGA_BIOS
+	default "1002,9641"
+
+config AHCI_BIOS
+	bool
+	default n
+
+#config AHCI_BIOS_FILE
+#	string "AHCI ROM path and filename"
+#	depends on AHCI_BIOS
+#	default "rom/ahci/sb900.bin"
+
+config AHCI_BIOS_ID
+	string "AHCI device PCI IDs"
+	depends on AHCI_BIOS
+	default "1022,7801"
+
+config XHC_BIOS
+	bool
+	default n
+
+#config XHC_BIOS_FILE
+#	string "XHC BIOS path and filename"
+#	depends on XHC_BIOS
+#	default "rom/xhc/Xhc.rom"
+
+config XHC_BIOS_ID
+	string "XHC device PCI IDs"
+	depends on XHC_BIOS
+	default "1022,7812"
+
+config CONSOLE_POST
+	bool
+	depends on !NO_POST
+	default y
+
+config SATA_CONTROLLER_MODE
+	hex
+	default 0x0
+	depends on SOUTHBRIDGE_AMD_CIMX_SB900
+
+config ONBOARD_LAN
+	bool
+	default y
+
+config ONBOARD_1394
+	bool
+	default y
+
+config ONBOARD_USB30
+	bool
+	default n
+
+config ONBOARD_BLUETOOTH
+	bool
+	default y
+
+config ONBOARD_WEBCAM
+	bool
+	default y
+
+config ONBOARD_TRAVIS
+	bool
+	default y
+
+config ONBOARD_LIGHTSENSOR
+	bool
+	default n
+
+endif # BOARD_AMD_TORPEDO
+

src/mainboard/amd/torpedo/Makefile.inc

@@ -0,0 +1,38 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+romstage-y += cfg.c
+romstage-y += gpio.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+ramstage-y += cfg.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
+
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12

src/mainboard/amd/torpedo/Oem.h

@@ -0,0 +1,259 @@
+/*;********************************************************************************
+;
+; Copyright 2011 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+;
+; AMD is granting you permission to use this software (the Materials)
+; pursuant to the terms and conditions of your Software License Agreement
+; with AMD.  This header does *NOT* give you permission to use the Materials
+; or any rights under AMD's intellectual property.  Your use of any portion
+; of these Materials shall constitute your acceptance of those terms and
+; conditions.  If you do not agree to the terms and conditions of the Software
+; License Agreement, please do not use any portion of these Materials.
+;
+; CONFIDENTIALITY:  The Materials and all other information, identified as
+; confidential and provided to you by AMD shall be kept confidential in
+; accordance with the terms and conditions of the Software License Agreement.
+;
+; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+; THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+; THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+;
+; AMD does not assume any responsibility for any errors which may appear in
+; the Materials or any other related information provided to you by AMD, or
+; result from use of the Materials or any related information.
+;
+; You agree that you will not reverse engineer or decompile the Materials.
+;
+; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+; further information, software, technical information, know-how, or show-how
+; available to you.  Additionally, AMD retains the right to modify the
+; Materials at any time, without notice, and is not obligated to provide such
+; modified Materials to you.
+;
+; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+; subject to the restrictions as set forth in FAR 52.227-14 and
+; DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+; Government constitutes acknowledgement of AMD's proprietary rights in them.
+;
+; EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+; direct product thereof will be exported directly or indirectly, into any
+; country prohibited by the United States Export Administration Act and the
+; regulations thereunder, without the required authorization from the U.S.
+; government nor will be used for any purpose prohibited by the same.
+;*********************************************************************************/
+
+#define BIOS_SIZE                      0x04   //04 - 1MB
+#define LEGACY_FREE                    0x00
+#if CONFIG_ONBOARD_USB30 == 0
+  #define XHCI_SUPPORT                 0x01
+#endif
+
+//#define ACPI_SLEEP_TRAP                0x01	// No sleep trap smi support in coreboot.
+//#define SPREAD_SPECTRUM_EPROM_LOAD     0x01
+
+/**
+ * Module Specific Defines for platform BIOS
+ *
+ */
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef  MOVE_PCIEBAR_TO_F0000000
+  #define PCIEX_BASE_ADDRESS           0xF7000000
+#else
+  #define PCIEX_BASE_ADDRESS           0xE0000000
+#endif
+
+/**
+ * SMBUS0_BASE_ADDRESS - Smbus base address
+ *
+ */
+#ifndef SMBUS0_BASE_ADDRESS
+  #define SMBUS0_BASE_ADDRESS          0xB00
+#endif
+
+/**
+ * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
+ *
+ */
+#ifndef SMBUS1_BASE_ADDRESS
+  #define SMBUS1_BASE_ADDRESS          0xB20
+#endif
+
+/**
+ * SIO_PME_BASE_ADDRESS - Super IO PME base address
+ *
+ */
+#ifndef SIO_PME_BASE_ADDRESS
+  #define SIO_PME_BASE_ADDRESS         0xE00
+#endif
+
+/**
+ * SPI_BASE_ADDRESS - SPI controller (ROM) base address
+ *
+ */
+#ifndef SPI_BASE_ADDRESS
+  #define SPI_BASE_ADDRESS             0xFEC10000
+#endif
+
+/**
+ * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
+ *
+ */
+#ifndef WATCHDOG_TIMER_BASE_ADDRESS
+  #define WATCHDOG_TIMER_BASE_ADDRESS  0xFEC000F0        // Watchdog Timer Base Address
+#endif
+
+/**
+ * HPET_BASE_ADDRESS - HPET base address
+ *
+ */
+#ifndef HPET_BASE_ADDRESS
+  #define HPET_BASE_ADDRESS            0xFED00000        // HPET Base address
+#endif
+
+/**
+ * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
+ *
+ */
+#ifdef ALT_ADDR_400
+  #define ACPI_BLK_BASE                0x400
+#else
+  #define ACPI_BLK_BASE                0x800
+#endif
+
+#define PM1_STATUS_OFFSET              0x00
+#define PM1_ENABLE_OFFSET              0x02
+#define PM1_CONTROL_OFFSET             0x04
+#define PM_TIMER_OFFSET                0x08
+#define CPU_CONTROL_OFFSET             0x10
+#define EVENT_STATUS_OFFSET            0x20
+#define EVENT_ENABLE_OFFSET            0x24
+
+/**
+ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
+ *
+ */
+#define PM1_EVT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_STATUS_OFFSET     // AcpiPm1EvtBlkAddr
+
+/**
+ * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
+ *
+ */
+#define PM1_CNT_BLK_ADDRESS           ACPI_BLK_BASE + PM1_CONTROL_OFFSET    // AcpiPm1CntBlkAddr
+
+/**
+ * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
+ *
+ */
+#define PM1_TMR_BLK_ADDRESS           ACPI_BLK_BASE + PM_TIMER_OFFSET       // AcpiPmTmrBlkAddr
+
+/**
+ * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
+ *
+ */
+#define CPU_CNT_BLK_ADDRESS           ACPI_BLK_BASE + CPU_CONTROL_OFFSET    // CpuControlBlkAddr
+
+/**
+ * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
+ *
+ */
+#define GPE0_BLK_ADDRESS              ACPI_BLK_BASE + EVENT_STATUS_OFFSET   // AcpiGpe0BlkAddr
+
+/**
+ * SMI_CMD_PORT - ACPI SMI Command block base address
+ *
+ */
+#define SMI_CMD_PORT                  0xB0              // SmiCmdPortAddr
+
+/**
+ * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
+ *
+ */
+#define ACPI_PMA_CNT_BLK_ADDRESS      0xFE00            // AcpiPmaCntBlkAddr
+
+/**
+ * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
+ *    Define value for SSID while SATA controller set to IDE mode.
+ */
+#define SATA_IDE_MODE_SSID           0x78001022
+/**
+ * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
+ *    Define value for SSID while SATA controller set to RAID mode.
+ */
+#define SATA_RAID_MODE_SSID          0x78021022
+
+/**
+ * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
+ *    Define value for SSID while SATA controller set to RAID5 mode.
+ */
+#define SATA_RAID5_MODE_SSID         0x78031022
+
+/**
+ * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
+ *    Define value for SSID while SATA controller set to AHCI mode.
+ */
+#define SATA_AHCI_SSID               0x78011022
+
+/**
+ * OHCI_SSID - All SB OHCI controllers SSID value.
+ *
+ */
+#define OHCI_SSID                    0x78071022
+
+/**
+ * EHCI_SSID - All SB EHCI controllers SSID value.
+ *
+ */
+#define EHCI_SSID                    0x78081022
+
+/**
+ * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
+ *
+ */
+#define OHCI4_SSID                   0x78091022
+
+/**
+ * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
+ *
+ */
+#define SMBUS_SSID                   0x780B1022
+
+/**
+ * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
+ *
+ */
+#define IDE_SSID                     0x780C1022
+
+/**
+ * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
+ *
+ */
+#define AZALIA_SSID                  0x780D1022
+
+/**
+ * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
+ *
+ */
+#define LPC_SSID                     0x780E1022
+
+/**
+ * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
+ *
+ */
+#define PCIB_SSID                    0x780F1022
+

src/mainboard/amd/torpedo/OptionsIds.h

@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 12067 $   @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED     TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_ASSERT_ENABLED  TRUE
+
+//#define IDSOPT_DEBUG_ENABLED  FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW    FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT       FALSE
+//#define IDS_DEBUG_PORT    0x80
+
+#endif

src/mainboard/amd/torpedo/PlatformGnbPcie.c

@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+			// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+			{
+			  0,   //Descriptor flags
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
+			},
+			// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+			{
+			  0,   //Descriptor flags
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
+			},
+			// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+			{
+			  0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+			},
+			// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+			{
+			  0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+			},
+			// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+			{
+			  0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+			},
+			// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+			{
+			  DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+			}
+			// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+//			{
+//			  DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+//			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
+//			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+//			}
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+			// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
+			{
+			  0,   //Descriptor flags
+			  PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+			  PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+			},
+			// Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
+			{
+			  DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			  PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+			  PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
+			}
+};
+
+PCIe_COMPLEX_DESCRIPTOR Llano = {
+        DESCRIPTOR_TERMINATE_LIST,
+        0,
+        &PortList[0],
+        &DdiList[0]
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the binary block
+ *    interface (call-out port) to provide a user hook opportunity
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+  IN  OUT AMD_EARLY_PARAMS    *InitEarly
+  )
+{
+  AGESA_STATUS         Status;
+  VOID                 *LlanoPcieComplexListPtr;
+  VOID                 *LlanoPciePortPtr;
+  VOID                 *LlanoPcieDdiPtr;
+
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // GNB PCIe topology Porting
+
+  //
+  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+  //
+  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+                                         sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
+                                         sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
+
+  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+  if ( Status!= AGESA_SUCCESS) {
+    // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+    ASSERT(FALSE);
+    return;
+  }
+
+  LlanoPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+  AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+  LlanoPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+  AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
+  LlanoPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+  LibAmdMemFill (LlanoPcieComplexListPtr,
+                   0,
+                   sizeof (PCIe_COMPLEX_DESCRIPTOR),
+                   &InitEarly->StdHeader);
+
+  LibAmdMemFill (LlanoPciePortPtr,
+                   0,
+                   sizeof (PCIe_PORT_DESCRIPTOR) * 7,
+                   &InitEarly->StdHeader);
+
+  LibAmdMemFill (LlanoPcieDdiPtr,
+                   0,
+                   sizeof (PCIe_DDI_DESCRIPTOR) * 6,
+                   &InitEarly->StdHeader);
+
+  LibAmdMemCopy  (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+  LibAmdMemCopy  (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
+  LibAmdMemCopy  (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
+
+
+  ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
+  ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
+
+  InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
+  InitEarly->GnbConfig.PsppPolicy      = 0;
+}
+

src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h

@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable  
+#define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) 
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+  IN  OUT AMD_EARLY_PARAMS    *InitEarly
+  );
+  
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

src/mainboard/amd/torpedo/acpi/cpstate.asl

@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}

src/mainboard/amd/torpedo/acpi/ide.asl

@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}

src/mainboard/amd/torpedo/acpi/routing.asl

@@ -0,0 +1,311 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
+		/* Bus 0, Dev 2 - */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		/* SB devices */
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+		Package(){0x0010FFFF, 0, INTC, 0 },
+		Package(){0x0010FFFF, 1, INTB, 0 },
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		Package(){0x0001FFFF, 1, 0, 19 },
+		/* Bus 0, Dev 2 */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		Package(){0x0002FFFF, 1, 0, 19 },
+		Package(){0x0002FFFF, 2, 0, 16 },
+		Package(){0x0002FFFF, 3, 0, 17 },
+		/* Bus 0, Dev 3 */
+		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+		Package(){0x0010FFFF, 0, 0, 18 },
+		Package(){0x0010FFFF, 1, 0, 17 },
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PS2, Package(){
+		/* For Device(PBR2) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* For Device(PBR2) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS3, Package(){
+		/* For Device(PBR3) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS3, Package(){
+		/* For Device(PBR3) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS4, Package(){
+		/* For Device(PBR4) PIC mode*/
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* For Device(PBR4) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* For Device(PBR5) PIC mode*/
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* For Device(PBR5) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* For Device(PBR6) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* For Device(PBR6) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* For Device(PBR7) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* For Device(PBR7) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PE0, Package(){
+		/* For Device(PE20) PIC mode*/
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APE0, Package(){
+		/* For Device(PE20) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* For Device(PE21) PIC mode*/
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APE1, Package(){
+		/* For Device(PE21) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* For Device(PE22) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APE2, Package(){
+		/* For Device(PE22) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* For Device(PE23) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APE3, Package(){
+		/* For Device(PE23) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+}

src/mainboard/amd/torpedo/acpi/sata.asl

@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}

src/mainboard/amd/torpedo/acpi/ssdt2.asl

@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+		// BUS ? Second HT Chain
+		Name (HCIN, 0xcc)  // HC2 0x01
+
+		Name (_UID,	 0xdd)	// HC 0x03
+
+		Name (_HID, "PNP0A03")
+
+		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+		{
+			Return (DADD(GHCN(HCIN), 0x00000000))
+		}
+
+		Method (_BBN, 0, NotSerialized)
+		{
+			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+		}
+
+		Method (_STA, 0, NotSerialized)
+		{
+			Return (\_SB.GHCE(HCIN))
+		}
+
+		Method (_CRS, 0, NotSerialized)
+		{
+			Name (BUF0, ResourceTemplate () { })
+			Store( GHCN(HCIN), Local4)
+			Store( GHCL(HCIN), Local5)
+
+			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+			Return (Local3)
+		}
+
+			#include "acpi/pci2_hc.asl"
+		}
+	}
+
+}
+

src/mainboard/amd/torpedo/acpi/ssdt3.asl

@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci3_hc.asl"
+		}
+	}
+
+}
+

src/mainboard/amd/torpedo/acpi/ssdt4.asl

@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+		External (DADD, MethodObj)
+		External (GHCE, MethodObj)
+		External (GHCN, MethodObj)
+		External (GHCL, MethodObj)
+		External (GHCD, MethodObj)
+		External (GNUS, MethodObj)
+		External (GIOR, MethodObj)
+		External (GMEM, MethodObj)
+		External (GWBN, MethodObj)
+		External (GBUS, MethodObj)
+
+		External (PICF)
+
+		External (\_SB.PCI0.LNKA, DeviceObj)
+		External (\_SB.PCI0.LNKB, DeviceObj)
+		External (\_SB.PCI0.LNKC, DeviceObj)
+		External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci4_hc.asl"
+		}
+	}
+
+}
+

src/mainboard/amd/torpedo/acpi/ssdt5.asl

@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
+{
+	Scope (_SB)
+	{
+	External (DADD, MethodObj)
+	External (GHCE, MethodObj)
+	External (GHCN, MethodObj)
+	External (GHCL, MethodObj)
+	External (GHCD, MethodObj)
+	External (GNUS, MethodObj)
+	External (GIOR, MethodObj)
+	External (GMEM, MethodObj)
+	External (GWBN, MethodObj)
+	External (GBUS, MethodObj)
+
+	External (PICF)
+
+	External (\_SB.PCI0.LNKA, DeviceObj)
+	External (\_SB.PCI0.LNKB, DeviceObj)
+	External (\_SB.PCI0.LNKC, DeviceObj)
+	External (\_SB.PCI0.LNKD, DeviceObj)
+
+		Device (PCIX)
+		{
+
+			// BUS ? Second HT Chain
+			Name (HCIN, 0xcc)  // HC2 0x01
+
+			Name (_UID,	 0xdd)	// HC 0x03
+
+			Name (_HID, "PNP0A03")
+
+			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+			{
+				Return (DADD(GHCN(HCIN), 0x00000000))
+			}
+
+			Method (_BBN, 0, NotSerialized)
+			{
+				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+			}
+
+			Method (_STA, 0, NotSerialized)
+			{
+				Return (\_SB.GHCE(HCIN))
+			}
+
+			Method (_CRS, 0, NotSerialized)
+			{
+				Name (BUF0, ResourceTemplate () { })
+				Store( GHCN(HCIN), Local4)
+				Store( GHCL(HCIN), Local5)
+
+				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+				Return (Local3)
+			}
+
+			#include "acpi/pci5_hc.asl"
+		}
+	}
+
+}
+

src/mainboard/amd/torpedo/acpi/usb.asl

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+

src/mainboard/amd/torpedo/acpi_tables.c

@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+extern u32 apicid_sb900;
+
+
+#if DUMP_ACPI_TABLES == 1
+
+static void dump_mem(u32 start, u32 end)
+{
+
+  u32 i;
+  print_debug("dump_mem:");
+  for (i = start; i < end; i++) {
+    if ((i & 0xf) == 0) {
+      printk(BIOS_DEBUG, "\n%08x:", i);
+    }
+    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+  }
+  print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+  /* Just a dummy */
+  return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+  
+  /* create all subtables for processors */
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 2);
+  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 3);
+  
+  /* Write SB900 IOAPIC, only one */
+  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900,
+             IO_APIC_ADDR, 0);
+
+  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+            current, 0, 0, 2, 0);
+  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+            current, 0, 9, 9, 0xF);
+  
+  /* 0: mean bus 0--->ISA */
+  /* 0: PIC 0 */
+  /* 2: APIC 2 */
+  /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+  /* create all subtables for processors */
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 2, 5, 1);
+  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 3, 5, 1);
+  /* 1: LINT1 connect to NMI */
+
+  return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+  // Not implemented
+  return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+  /* No NUMA, no SRAT */
+  return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+  unsigned long current;
+  acpi_rsdp_t *rsdp;
+  acpi_rsdt_t *rsdt;
+  acpi_hpet_t *hpet;
+  acpi_madt_t *madt;
+  acpi_srat_t *srat;
+  acpi_slit_t *slit;
+  acpi_fadt_t *fadt;
+  acpi_facs_t *facs;
+  acpi_header_t *dsdt;
+  acpi_header_t *ssdt;
+
+  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+  /* Align ACPI tables to 16 bytes */
+  start = (start + 0x0f) & -0x10;
+  current = start;
+
+  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+  /* We need at least an RSDP and an RSDT Table */
+  rsdp = (acpi_rsdp_t *) current;
+  current += sizeof(acpi_rsdp_t);
+  rsdt = (acpi_rsdt_t *) current;
+  current += sizeof(acpi_rsdt_t);
+
+  /* clear all table memory */
+  memset((void *)start, 0, current - start);
+
+  acpi_write_rsdp(rsdp, rsdt, NULL);
+  acpi_write_rsdt(rsdt);
+
+  /*
+   * We explicitly add these tables later on:
+   */
+#if 0 // Don't need HPET table.
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+  hpet = (acpi_hpet_t *) current;
+  current += sizeof(acpi_hpet_t);
+  acpi_create_hpet(hpet);
+  acpi_add_table(rsdp, hpet);
+#endif
+
+  /* If we want to use HPET Timers Linux wants an MADT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+  madt = (acpi_madt_t *) current;
+  acpi_create_madt(madt);
+  current += madt->header.length;
+  acpi_add_table(rsdp, madt);
+
+  /* SRAT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+  if (srat != NULL) {
+    memcpy(current, srat, srat->header.length);
+    srat = (acpi_srat_t *) current;
+    //acpi_create_srat(srat);
+    current += srat->header.length;
+    acpi_add_table(rsdp, srat);
+  }
+
+  /* SLIT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+  if (slit != NULL) {
+    memcpy(current, slit, slit->header.length);
+    slit = (acpi_slit_t *) current;
+    //acpi_create_slit(slit);
+    current += slit->header.length;
+    acpi_add_table(rsdp, slit);
+  }
+
+  /* SSDT */
+  current   = ( current + 0x0f) & -0x10;
+  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+  if (ssdt != NULL) {
+    memcpy(current, ssdt, ssdt->length);
+    ssdt = (acpi_header_t *) current;
+    current += ssdt->length;
+  }
+  else {
+    ssdt = (acpi_header_t *) current;
+    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+    current += ssdt->length;
+    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+   /* recalculate checksum */
+    ssdt->checksum = 0;
+    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+  }
+  acpi_add_table(rsdp,ssdt);
+
+  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+
+  /* DSDT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+  dsdt = (acpi_header_t *)current; // it will used by fadt
+  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+  current += dsdt->length;
+  memcpy(dsdt, &AmlCode, dsdt->length);
+  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+  /* FACS */ // it needs 64 bit alignment
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+  facs = (acpi_facs_t *) current; // it will be used by fadt
+  current += sizeof(acpi_facs_t);
+  acpi_create_facs(facs);
+
+  /* FADT */
+  current   = ( current + 0x07) & -0x08;
+  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+  fadt = (acpi_fadt_t *) current;
+  current += sizeof(acpi_fadt_t);
+
+  acpi_create_fadt(fadt, facs, dsdt);
+  acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+  printk(BIOS_DEBUG, "rsdp\n");
+  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+  printk(BIOS_DEBUG, "rsdt\n");
+  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+  printk(BIOS_DEBUG, "madt\n");
+  dump_mem(madt, ((void *)madt) + madt->header.length);
+
+  printk(BIOS_DEBUG, "srat\n");
+  dump_mem(srat, ((void *)srat) + srat->header.length);
+
+  printk(BIOS_DEBUG, "slit\n");
+  dump_mem(slit, ((void *)slit) + slit->header.length);
+
+  printk(BIOS_DEBUG, "ssdt\n");
+  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+  printk(BIOS_DEBUG, "fadt\n");
+  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+  printk(BIOS_INFO, "ACPI: done.\n");
+  return current;
+}

src/mainboard/amd/torpedo/agesawrapper.c

@@ -0,0 +1,584 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+#include <arch/io.h>
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable    = NULL;
+VOID *AcpiPstate  = NULL;
+VOID *AcpiSrat    = NULL;
+VOID *AcpiSlit    = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib    = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+ReadAmdSbPmr (
+  IN     UINT8                      IndexValue,
+  OUT    UINT8                      *DataValue
+  );
+
+UINT32
+WriteAmdSbPmr (
+  IN     UINT8                      IndexValue,
+  IN     UINT8                      DataValue
+  );
+
+VOID
+ClearSBSmiAndWake (
+  IN UINT16             PmBase
+  );
+
+VOID
+ClearAllSmiEnableInPmio (
+  VOID
+  );
+
+
+
+/* Read SB Power Management Area */
+UINT32
+ReadAmdSbPmr (
+  IN     UINT8                      IndexValue,
+  OUT    UINT8                      *DataValue
+  )
+{
+  WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
+  *DataValue = ReadIo8 (SB_PM_DATA_PORT);
+  return 0;
+}
+
+/* Write ATI SB Power Management Area */
+UINT32
+WriteAmdSbPmr (
+  IN     UINT8                      IndexValue,
+  IN     UINT8                      DataValue
+  )
+{
+  WriteIo8 (SB_PM_INDEX_PORT, IndexValue);
+  WriteIo8 (SB_PM_DATA_PORT, DataValue);
+  return 0;
+}
+
+/* Clear any SMI status or wake status left over from boot. */
+VOID
+ClearSBSmiAndWake (
+  IN UINT16             PmBase
+  )
+{
+  UINT16  Pm1Sts;
+  UINT32  Pm1Cnt;
+  UINT32  Gpe0Sts;
+
+  /*  Read the ACPI registers */
+  Pm1Sts  = ReadIo16 (PmBase + R_SB_ACPI_PM1_STATUS);
+  Pm1Cnt  = ReadIo32 (PmBase + R_SB_ACPI_PM1_STATUS);
+  Gpe0Sts = ReadIo32 (PmBase + R_SB_ACPI_EVENT_STATUS);
+
+  /* Clear any SMI or wake state from the boot */
+  Pm1Sts &= B_PWR_BTN_STATUS + B_WAKEUP_STATUS;
+  Pm1Cnt &= ~(B_SCI_EN);
+
+  /* Write back */
+  WriteIo16 (PmBase + R_SB_ACPI_PM1_STATUS, Pm1Sts);
+  WriteIo32 (PmBase + R_SB_ACPI_PM_CONTROL, Pm1Cnt);
+  WriteIo32 (PmBase + R_SB_ACPI_EVENT_STATUS, Gpe0Sts);
+}
+
+/* Clear all SMI enable bit in PMIO register */
+VOID
+ClearAllSmiEnableInPmio (
+  VOID
+  )
+{
+  UINT32  AcpiMmioAddr;
+  UINT32  SmiMmioAddr;
+  UINT8   Data8 = 0 ;
+  UINT16  Data16 = 0;
+
+  /* Get SB900 MMIO Base (AcpiMmioAddr) */
+  ReadAmdSbPmr (SB_PMIOA_REG24 + 3, &Data8);
+  Data16=Data8<<8;
+  ReadAmdSbPmr (SB_PMIOA_REG24 + 2, &Data8);
+  Data16|=Data8;
+  AcpiMmioAddr = (UINT32)Data16 << 16;
+  SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
+
+  Mmio32 (SmiMmioAddr, 0xA0) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xA4) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xA8) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xAC) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xB0) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xB4) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xB8) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xBC) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xC0) = 0x0;
+  Mmio32 (SmiMmioAddr, 0xC4) = 0x0;
+}
+
+UINT32
+agesawrapper_amdinitcpuio (
+  VOID
+  )
+{
+  AGESA_STATUS                  Status;
+  UINT64                        MsrReg;
+  UINT32                        PciData;
+  PCI_ADDR                      PciAddress;
+  AMD_CONFIG_PARAMS             StdHeader;
+
+  /* Enable MMIO on AMD CPU Address Map Controller */
+
+  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+  PciData = 0x00000B00;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+  PciData = 0x00000A03;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+  /* Set TOM-DFFFFFFF to Node0 Link0. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+  PciData = 0x00DFFF00;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+  MsrReg = (MsrReg >> 8) | 3;
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+  PciData = (UINT32)MsrReg;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
+  PciData = 0x00FFFF00 | 0x80;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
+  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+//-  PciData = 0x0000F000;
+  PciData = 0x00FFF000;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+  PciData = 0x00000013;
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+  Status = AGESA_SUCCESS;
+  return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitmmio (
+  VOID
+  )
+{
+  AGESA_STATUS                  Status;
+  UINT64                        MsrReg;
+  UINT32                        PciData;
+  PCI_ADDR                      PciAddress;
+  AMD_CONFIG_PARAMS             StdHeader;
+
+  /*
+   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+   Address MSR register.
+  */
+  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+  /*
+   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+  */
+  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+  MsrReg = MsrReg | 0x0000400000000000ull;
+  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+  /* Set Ontario Link Data */
+//-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+//-  PciData = 0x01308002;
+//-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+//-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+//-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+//-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+  /* Enable Non-Post Memory in CPU */
+  PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA4);
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+  PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x018, 0x01, 0xA0);
+  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+  /* Enable memory access */
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+  LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+  PciData |= BIT1;
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+  LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+  /* Set ROM cache onto WP to decrease post time */
+  MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+  MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+  /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
+//-  ClearSBSmiAndWake (SB_ACPI_BASE_ADDRESS);
+//-  ClearAllSmiEnableInPmio ();
+
+  Status = AGESA_SUCCESS;
+  return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitreset (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  AMD_RESET_PARAMS AmdResetParams;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+
+  LibAmdMemFill (&AmdResetParams,
+                 0,
+                 sizeof (AMD_RESET_PARAMS),
+                 &(AmdResetParams.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+  AmdParamStruct.AllocationMethod = ByHost;
+  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+  AmdParamStruct.NewStructPtr = &AmdResetParams;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = NULL;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+  AmdResetParams.HtConfig.Depth = 0;
+
+  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+  return (UINT32)status;
+ }
+
+UINT32
+agesawrapper_amdinitearly (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+  AmdParamStruct.AllocationMethod = PreMemHeap;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+
+  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+  OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitpost (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  UINT16                  i;
+  UINT32          *HeadPtr;
+  AMD_INTERFACE_PARAMS  AmdParamStruct;
+  BIOS_HEAP_MANAGER    *BiosManagerPtr;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+  AmdParamStruct.AllocationMethod = PreMemHeap;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+  AmdCreateStruct (&AmdParamStruct);
+  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  /* Initialize heap space */
+  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+  {
+    *HeadPtr = 0x00000000;
+    HeadPtr++;
+  }
+  BiosManagerPtr->StartOfAllocatedNodes = 0;
+  BiosManagerPtr->StartOfFreedNodes = 0;
+
+  return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitenv (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+  AmdCreateStruct (&AmdParamStruct);
+  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+  int pick
+  )
+{
+  switch (pick) {
+    case PICK_DMI:
+      return DmiTable;
+
+    case PICK_PSTATE:
+      return AcpiPstate;
+
+    case PICK_SRAT:
+      return AcpiSrat;
+
+    case PICK_SLIT:
+      return AcpiSlit;
+    case PICK_WHEA_MCE:
+      return AcpiWheaMce;
+    case PICK_WHEA_CMC:
+      return AcpiWheaCmc;
+    case PICK_ALIB:
+      return AcpiAlib;
+    default:
+      return NULL;
+  }
+}
+
+UINT32
+agesawrapper_amdinitmid (
+  VOID
+  )
+{
+  AGESA_STATUS status;
+  AMD_INTERFACE_PARAMS AmdParamStruct;
+
+  /* Enable MMIO on AMD CPU Address Map Controller */
+  agesawrapper_amdinitcpuio ();
+
+  LibAmdMemFill (&AmdParamStruct,
+                 0,
+                 sizeof (AMD_INTERFACE_PARAMS),
+                 &(AmdParamStruct.StdHeader));
+
+  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+  AmdParamStruct.AllocationMethod = PostMemDram;
+  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdParamStruct.StdHeader.Func = 0;
+  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+  AmdCreateStruct (&AmdParamStruct);
+
+  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+  AmdReleaseStruct (&AmdParamStruct);
+
+  return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitlate (
+  VOID
+  )
+{
+  AGESA_STATUS Status;
+  AMD_LATE_PARAMS AmdLateParams;
+
+  LibAmdMemFill (&AmdLateParams,
+                 0,
+                 sizeof (AMD_LATE_PARAMS),
+                 &(AmdLateParams.StdHeader));
+
+  AmdLateParams.StdHeader.AltImageBasePtr = 0;
+  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  AmdLateParams.StdHeader.Func = 0;
+  AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+  Status = AmdInitLate (&AmdLateParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
+
+  DmiTable       = AmdLateParams.DmiTable;
+  AcpiPstate     = AmdLateParams.AcpiPState;
+  AcpiSrat       = AmdLateParams.AcpiSrat;
+  AcpiSlit       = AmdLateParams.AcpiSlit;
+
+  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
+  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
+  AcpiAlib       = AmdLateParams.AcpiAlib;
+
+  return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdlaterunaptask (
+  UINT32 Data,
+  VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  AP_EXE_PARAMS ApExeParams;
+
+  LibAmdMemFill (&ApExeParams,
+                 0,
+                 sizeof (AP_EXE_PARAMS),
+                 &(ApExeParams.StdHeader));
+
+  ApExeParams.StdHeader.AltImageBasePtr = 0;
+  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+  ApExeParams.StdHeader.Func = 0;
+  ApExeParams.StdHeader.ImageBasePtr = 0;
+
+  Status = AmdLateRunApTask (&ApExeParams);
+  if (Status != AGESA_SUCCESS) {
+    agesawrapper_amdreadeventlog();
+    ASSERT(Status == AGESA_SUCCESS);
+  }
+
+  return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdreadeventlog (
+  VOID
+  )
+{
+  AGESA_STATUS Status;
+  EVENT_PARAMS AmdEventParams;
+
+  LibAmdMemFill (&AmdEventParams,
+                 0,
+                 sizeof (EVENT_PARAMS),
+                 &(AmdEventParams.StdHeader));
+
+  AmdEventParams.StdHeader.AltImageBasePtr = 0;
+  AmdEventParams.StdHeader.CalloutPtr = NULL;
+  AmdEventParams.StdHeader.Func = 0;
+  AmdEventParams.StdHeader.ImageBasePtr = 0;
+  Status = AmdReadEventLog (&AmdEventParams);
+  while (AmdEventParams.EventClass != 0) {
+    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+    printk(BIOS_DEBUG,"  Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+    printk(BIOS_DEBUG,"  Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+    Status = AmdReadEventLog (&AmdEventParams);
+  }
+
+  return (UINT32)Status;
+}

src/mainboard/amd/torpedo/agesawrapper.h

@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID    0x1022
+#define AMD_APU_SSID    0x1234
+#define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
+
+/* Hudson-2 ACPI PmIO Space Define */
+#define SB_ACPI_BASE_ADDRESS              0x0400
+#define ACPI_MMIO_BASE  0xFED80000
+#define SB_CFG_BASE     0x000   // DWORD
+#define GPIO_BASE       0x100   // BYTE
+#define SMI_BASE        0x200   // DWORD
+#define PMIO_BASE       0x300   // DWORD
+#define PMIO2_BASE      0x400   // BYTE
+#define BIOS_RAM_BASE   0x500   // BYTE
+#define CMOS_RAM_BASE   0x600   // BYTE
+#define CMOS_BASE       0x700   // BYTE
+#define ASF_BASE        0x900   // DWORD
+#define SMBUS_BASE      0xA00   // DWORD
+#define WATCHDOG_BASE   0xB00   // ??
+#define HPET_BASE       0xC00   // DWORD
+#define IOMUX_BASE      0xD00   // BYTE
+#define MISC_BASE       0xE00
+#define SERIAL_DEBUG_BASE  0x1000
+#define GFX_DAC_BASE       0x1400
+#define CEC_BASE           0x1800
+#define XHCI_BASE          0x1C00
+#define ACPI_SMI_DATA_PORT                0xB1
+#define R_SB_ACPI_PM1_STATUS              0x00
+#define R_SB_ACPI_PM1_ENABLE              0x02
+#define R_SB_ACPI_PM_CONTROL              0x04
+#define R_SB_ACPI_EVENT_STATUS            0x20
+#define R_SB_ACPI_EVENT_ENABLE            0x24
+#define   B_PWR_BTN_STATUS                BIT8
+#define   B_WAKEUP_STATUS                 BIT15
+#define   B_SCI_EN                        BIT0
+#define SB_PM_INDEX_PORT                  0xCD6
+#define SB_PM_DATA_PORT                   0xCD7
+#define SB_PMIOA_REG24          0x24        //  AcpiMmioEn
+#define MmioAddress( BaseAddr, Register ) \
+  ( (UINTN)BaseAddr + \
+    (UINTN)(Register) \
+  )
+#define Mmio32Ptr( BaseAddr, Register ) \
+  ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+#define Mmio32( BaseAddr, Register ) \
+  *Mmio32Ptr( BaseAddr, Register )
+
+enum {
+  PICK_DMI,       /* DMI Interface */
+  PICK_PSTATE,    /* Acpi Pstate SSDT Table */
+  PICK_SRAT,      /* SRAT Table */
+  PICK_SLIT,      /* SLIT Table */
+  PICK_WHEA_MCE,  /* WHEA MCE table */
+  PICK_WHEA_CMC,  /* WHEA CMV table */
+  PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  UINT32 CalloutName;
+  AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+//void brazos_platform_stage(void);
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+
+UINT32 agesawrapper_amdreadeventlog (void);
+UINT32 agesawrapper_amdinitcpuio (void);
+UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Data, VOID *ConfigPtr);
+void *agesawrapper_getlateinitptr (int pick);
+
+#endif

src/mainboard/amd/torpedo/buildOpts.c

@@ -0,0 +1,387 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Sabine/Lynx platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+#include  "AGESA.h"
+#include  "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+
+/*  Select the cpu family.  */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT TRUE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_SUPPORT FALSE
+
+/*  Select the cpu socket type.  */
+#define INSTALL_G34_SOCKET_SUPPORT  FALSE
+#define INSTALL_C32_SOCKET_SUPPORT  FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT  TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT  TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT           FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT           FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT              FALSE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE          FALSE
+#define BLDOPT_REMOVE_DCT_INTERLEAVE           FALSE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      FALSE
+#define BLDOPT_REMOVE_DDR2_SUPPORT             TRUE
+#define BLDOPT_REMOVE_DDR3_SUPPORT             FALSE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
+#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
+#define BLDOPT_REMOVE_SRAT                     TRUE
+#define BLDOPT_REMOVE_SLIT                     TRUE
+#define BLDOPT_REMOVE_WHEA                     TRUE
+#define BLDOPT_REMOVE_DMI                      FALSE
+#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC         FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT         FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD         FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS         FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS        FALSE
+
+//For revision C single-link processors
+#define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX  TRUE
+
+/*
+ * Agesa entry points used in this implementation.
+ */
+#define AGESA_ENTRY_INIT_RESET                    TRUE
+#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
+#define AGESA_ENTRY_INIT_EARLY                    TRUE
+#define AGESA_ENTRY_INIT_POST                     TRUE
+#define AGESA_ENTRY_INIT_ENV                      TRUE
+#define AGESA_ENTRY_INIT_MID                      TRUE
+#define AGESA_ENTRY_INIT_LATE                     TRUE
+#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+#define AGESA_ENTRY_INIT_RESUME                   TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "LlanoPI "
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT                 65000  //240000 //120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD           15000  // 0
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
+#define BLDCFG_PLAT_NUM_IO_APICS                 3
+#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE                   0
+
+#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY //DDR1066_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
+#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
+#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE                       FALSE
+#define BLDCFG_MEMORY_PARITY_ENABLE               FALSE
+#define BLDCFG_BANK_SWIZZLE                       TRUE
+#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
+#define BLDCFG_USE_BURST_MODE                     FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
+#define BLDCFG_ECC_REDIRECTION                    FALSE
+#define BLDCFG_SCRUB_DRAM_RATE                    0
+#define BLDCFG_SCRUB_L2_RATE                      0
+#define BLDCFG_SCRUB_L3_RATE                      0
+#define BLDCFG_SCRUB_IC_RATE                      0
+#define BLDCFG_SCRUB_DC_RATE                      0
+#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
+#define BLDCFG_ECC_SYMBOL_SIZE                    4
+#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
+#define BLDCFG_1GB_ALIGN                          FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
+
+//enable HW C1E
+#define BLDCFG_PLATFORM_C1E_MODE     0 //C1eModeHardware
+//#define BLDCFG_PLATFORM_C1E_OPDATA              0x415
+#define BLDCFG_PLATFORM_CSTATE_MODE     CStateModeC6 //0 //CStateModeC6
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
+
+
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Llano/Ontario
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L.  Default is Zero.
+//#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime per BKDG.  Defaults to 5000, same as core VRM.  Cannot be zero.
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Llano/Ontario
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Llano/Ontario
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Llano/Ontario
+
+#define BLDCFG_UMA_ABOVE4G_SUPPORT              TRUE
+#define BLDCFG_STEREO_3D_PINOUT                 TRUE
+
+/*  Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
+{
+  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
+  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
+  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
+  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
+  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
+  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
+  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
+  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
+  { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
+//#define OPTION_NB_LCLK_DPM_INIT FALSE
+//#define OPTION_POWER_GATE       FALSE
+//#define OPTION_PCIE_POWER_GATE  FALSE
+//#define OPTION_ALIB             FALSE
+//#define OPTION_PCIe_MID_INIT  FALSE
+//#define OPTION_NB_MID_INIT    FALSE
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ *                        CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+  //
+  // The following macros are supported (use comma to separate macros):
+  //
+  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+  //      AGESA will base on this value to disable unused MemClk to save power.
+  //      Example:
+  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+  //           Bit AM3/S1g3 pin name
+  //           0   M[B,A]_CLK_H/L[0]
+  //           1   M[B,A]_CLK_H/L[1]
+  //           2   M[B,A]_CLK_H/L[2]
+  //           3   M[B,A]_CLK_H/L[3]
+  //           4   M[B,A]_CLK_H/L[4]
+  //           5   M[B,A]_CLK_H/L[5]
+  //           6   M[B,A]_CLK_H/L[6]
+  //           7   M[B,A]_CLK_H/L[7]
+  //      And platform has the following routing:
+  //           CS0   M[B,A]_CLK_H/L[4]
+  //           CS1   M[B,A]_CLK_H/L[2]
+  //           CS2   M[B,A]_CLK_H/L[3]
+  //           CS3   M[B,A]_CLK_H/L[5]
+  //      Then platform can specify the following macro:
+  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+  //
+  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+  //      AGESA will base on this value to tristate unused CKE to save power.
+  //
+  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+  //      AGESA will base on this value to tristate unused ODT pins to save power.
+  //
+  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+  //      AGESA will base on this value to tristate unused Chip select to save power.
+  //
+  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+  //      Specifies the number of DIMM slots per channel.
+  //
+  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+  //      Specifies the number of Chip selects per channel.
+  //
+  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+  //      Specifies the number of channels per socket.
+  //
+  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
+  //
+  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+  //
+  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+  //      Byte6Seed, Byte7Seed, ByteEccSeed)
+  //      Specifies the write leveling seed for a channel of a socket.
+  //
+  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+  PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//DA Customer table
+UINT8 AGESA_MEM_TABLE_LN[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ //   NOTE:
+ //   The following training hardcode values are example values that were taken from a tilapia motherboard
+ //   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
+ //   the table and replace the byte lane values with your own.
+ //
+ //                                                                               ------------------ BYTE LANES ----------------------
+ //                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+ // Write Data Timing
+  // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x15, 0x14, 0x21, 0x11, 0x40, 0x2A, 0x34, 0x2D, 0x15),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+  // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x17, 0x16, 0x21, 0x11, 0x3F, 0x2A, 0x35, 0x2E, 0x17),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+  // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x77, 0x70, 0x77, 0x60, 0x95, 0x83, 0x8F, 0x90, 0x77),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+  // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x7D, 0x75, 0x7F, 0x6C, 0x9A, 0x8D, 0x94, 0x98, 0x7D),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+  // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x03, 0x04, 0x0F, 0x00, 0x2D, 0x1B, 0x23, 0x1C, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+  // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x05, 0x05, 0x0F, 0x00, 0x2E, 0x19, 0x24, 0x1C, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+  // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x0C, 0x0A, 0x0A, 0x0E, 0x0A, 0x0C, 0x0C, 0x0A, 0x0C),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+  // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x0A, 0x0C, 0x0E, 0x0A, 0x0C, 0x0A, 0x0C, 0x0E, 0x0A),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ // --------------------------------------------------------------------------------------------------------------------------------------------------
+
+ // MaxRdLatency
+  // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct0, BFMaxLatency, MTOverride, 0x0C),
+  // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct1, BFMaxLatency, MTOverride, 0x0C),
+ // TABLE END
+  NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+};
+UINT8 SizeOfTableLN = sizeof (AGESA_MEM_TABLE_LN) / sizeof (AGESA_MEM_TABLE_LN[0]);
+
+/* ***************************************************************************
+ *   Optional User code to be included into the AGESA build
+ *    These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+//  IN        UINTN                 FcnData,
+//  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+//  )
+//{
+//  /* platform code to read an SPD...  */
+//  return Status;
+//}
+
+

src/mainboard/amd/torpedo/cfg.c

@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <string.h>
+#include "SbPlatform.h"
+#include "cfg.h"
+#include <console/console.h>	/* printk */
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb900_cimx_config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+        printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+		return;
+	}
+    printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
+	memset(sb_config, 0, sizeof(AMDSBCFG));
+
+	/* static Build Parameters */
+	sb_config->BuildParameters.BiosSize				= BIOS_SIZE;
+	sb_config->BuildParameters.LegacyFree			= LEGACY_FREE;
+	sb_config->BuildParameters.WatchDogTimerBase	= WATCHDOG_TIMER_BASE_ADDRESS;	// Board Level
+	sb_config->BuildParameters.AcpiGpe0BlkAddr		= GPE0_BLK_ADDRESS;				// Board Level
+	sb_config->BuildParameters.CpuControlBlkAddr	= CPU_CNT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr		= PM1_TMR_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr	= PM1_CNT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr	= PM1_EVT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.SioPmeBaseAddress	= SIO_PME_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.SpiRomBaseAddress	= SPI_BASE_ADDRESS;				// Board Level
+	sb_config->BuildParameters.Smbus0BaseAddress	= SMBUS0_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.Smbus1BaseAddress	= SMBUS1_BASE_ADDRESS;			// Board Level
+
+	/* Turn on CDROM and HDD Power */
+	sb_config->SATAMODE.SataMode.SataClkMode		= SATA_CLK_RESERVED;
+
+	// header
+	sb_config->StdHeader.PcieBasePtr				= PCIEX_BASE_ADDRESS;
+
+	// Build Parameters
+	sb_config->BuildParameters.ImcEnableOverWrite	= IMC_ENABLE_OVER_WRITE;		// Internal Option
+	sb_config->BuildParameters.UsbMsi				= USB_MSI;						// Internal Option
+	sb_config->BuildParameters.HdAudioMsi			= HDAUDIO_MSI;					// Internal Option
+	sb_config->BuildParameters.LpcMsi				= LPC_MSI;						// Internal Option
+	sb_config->BuildParameters.PcibMsi				= PCIB_MSI;						// Internal Option
+	sb_config->BuildParameters.AbMsi				= AB_MSI;						// Internal Option
+	sb_config->BuildParameters.GecShadowRomBase		= GEC_SHADOWROM_BASE;			// Board Level
+	sb_config->BuildParameters.HpetBase				= HPET_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.SataIDESsid			= SATA_IDE_MODE_SSID;			// Board Level
+	sb_config->BuildParameters.SataRAIDSsid			= SATA_RAID_MODE_SSID;			// Board Level
+	sb_config->BuildParameters.SataRAID5Ssid		= SATA_RAID5_MODE_SSID;			// Board Level
+	sb_config->BuildParameters.SataAHCISsid			= SATA_AHCI_SSID;				// Board Level
+	sb_config->BuildParameters.OhciSsid				= OHCI_SSID;					// Board Level
+	sb_config->BuildParameters.EhciSsid				= EHCI_SSID;					// Board Level
+	sb_config->BuildParameters.Ohci4Ssid			= OHCI4_SSID;					// Board Level
+	sb_config->BuildParameters.SmbusSsid			= SMBUS_SSID;					// Board Level
+	sb_config->BuildParameters.IdeSsid				= IDE_SSID;						// Board Level
+	sb_config->BuildParameters.AzaliaSsid			= AZALIA_SSID;					// Board Level
+	sb_config->BuildParameters.LpcSsid				= LPC_SSID;						// Board Level
+	// sb_config->BuildParameters.PCIBSsid				= PCIB_SSID;					// Field Retired
+
+	//
+	// Common Function
+	//
+	sb_config->SATAMODE.SataMode.SataController		= SATA_CONTROLLER;				// External Option
+	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt	= SATA_IDE_COMBMD_PRISEC_OPT;	// External Option
+	sb_config->SATAMODE.SataMode.SataIdeCombinedMode	= SATA_IDECOMBINED_MODE;	// External Option
+	sb_config->S3Resume								= 0;							// CIMx Internal Used
+	sb_config->SpreadSpectrum						= INCHIP_SPREAD_SPECTRUM;		// Board Level
+	sb_config->NbSbGen2								= INCHIP_NB_SB_GEN2;			// External Option
+	sb_config->GppGen2								= INCHIP_GPP_GEN2;				// External Option
+	sb_config->GppMemWrImprove						= INCHIP_GPP_MEMORY_WRITE_IMPROVE;	// Internal Option
+	sb_config->S4Resume								= 0;							// CIMx Internal Used
+	sb_config->SataClass							= CONFIG_SATA_CONTROLLER_MODE;	// INCHIP_SATA_MODE	// External Option
+	sb_config->SataIdeMode							= INCHIP_IDE_MODE;				// External Option
+	sb_config->sdConfig								= SB_SD_CONFIG;					// External Option
+	sb_config->sdSpeed								= SB_SD_SPEED;					// Internal Option
+	sb_config->sdBitwidth							= SB_SD_BITWIDTH;				// Internal Option
+	sb_config->SataDisUnusedIdePChannel				= SATA_DISUNUSED_IDE_P_CHANNEL;	// External Option
+	sb_config->SataDisUnusedIdeSChannel				= SATA_DISUNUSED_IDE_S_CHANNEL;	// External Option
+	sb_config->IdeDisUnusedIdePChannel				= IDE_DISUNUSED_IDE_P_CHANNEL;	// External Option
+	sb_config->IdeDisUnusedIdeSChannel				= IDE_DISUNUSED_IDE_S_CHANNEL;	// External Option
+	sb_config->SATAESPPORT.SataEspPort.PORT0		= SATA_ESP_PORT0;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT1		= SATA_ESP_PORT1;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT2		= SATA_ESP_PORT2;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT3		= SATA_ESP_PORT3;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT4		= SATA_ESP_PORT4;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT5		= SATA_ESP_PORT5;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT6		= SATA_ESP_PORT6;				// Board Level
+	sb_config->SATAESPPORT.SataEspPort.PORT7		= SATA_ESP_PORT7;				// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT0	= SATA_PORT_POWER_PORT0;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT1	= SATA_PORT_POWER_PORT1;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT2	= SATA_PORT_POWER_PORT2;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT3	= SATA_PORT_POWER_PORT3;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT4	= SATA_PORT_POWER_PORT4;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT5	= SATA_PORT_POWER_PORT5;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT6	= SATA_PORT_POWER_PORT6;		// Board Level
+	sb_config->SATAPORTPOWER.SataPortPower.PORT7	= SATA_PORT_POWER_PORT7;		// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT0		= SATA_PORTMODE_PORT0;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT1		= SATA_PORTMODE_PORT1;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT2		= SATA_PORTMODE_PORT2;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT3		= SATA_PORTMODE_PORT3;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT4		= SATA_PORTMODE_PORT4;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT5		= SATA_PORTMODE_PORT5;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT6		= SATA_PORTMODE_PORT6;			// Board Level
+	sb_config->SATAPORTMODE.SataPortMd.PORT7		= SATA_PORTMODE_PORT7;			// Board Level
+	sb_config->SataAggrLinkPmCap					= INCHIP_SATA_AGGR_LINK_PM_CAP;	// Internal Option
+	sb_config->SataPortMultCap						= INCHIP_SATA_PORT_MULT_CAP;	// Internal Option
+	sb_config->SataClkAutoOff						= INCHIP_SATA_CLK_AUTO_OFF;		// External Option
+	sb_config->SataPscCap							= INCHIP_SATA_PSC_CAP;			// External Option
+	sb_config->SataFisBasedSwitching				= INCHIP_SATA_FIS_BASE_SW;		// External Option
+	sb_config->SataCccSupport						= INCHIP_SATA_CCC_SUPPORT;		// External Option
+	sb_config->SataSscCap							= INCHIP_SATA_SSC_CAP;			// External Option
+	sb_config->SataMsiCapability					= INCHIP_SATA_MSI_CAP;			// Internal Option
+	sb_config->SataForceRaid						= INCHIP_SATA_FORCE_RAID5;		// Internal Option
+	sb_config->SataTargetSupport8Device				= CIMXSB_SATA_TARGET_8DEVICE_CAP;	// External Option
+	sb_config->SataDisableGenericMode				= SATA_DISABLE_GENERIC_MODE_CAP;// External Option
+	sb_config->SataAhciEnclosureManagement			= SATA_AHCI_ENCLOSURE_CAP;		// Internal Option
+	sb_config->SataSgpio0							= SATA_GPIO_0_CAP;				// External Option
+	sb_config->SataSgpio1							= SATA_GPIO_1_CAP;				// External Option
+	sb_config->SataPhyPllShutDown					= SATA_PHY_PLL_SHUTDOWN;		// External Option
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0	= SATA_HOTREMOVEL_ENH_PORT0;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1	= SATA_HOTREMOVEL_ENH_PORT1;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2	= SATA_HOTREMOVEL_ENH_PORT2;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3	= SATA_HOTREMOVEL_ENH_PORT3;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4	= SATA_HOTREMOVEL_ENH_PORT4;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5	= SATA_HOTREMOVEL_ENH_PORT5;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6	= SATA_HOTREMOVEL_ENH_PORT6;	// Board Level
+	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7	= SATA_HOTREMOVEL_ENH_PORT7;	// Board Level
+	// USB
+	sb_config->USBMODE.UsbMode.Ohci1				= INCHIP_USB_OHCI1_CINFIG;		// External Option
+	sb_config->USBMODE.UsbMode.Ehci1				= INCHIP_USB_EHCI1_CINFIG;		// Internal Option*
+	sb_config->USBMODE.UsbMode.Ohci2				= INCHIP_USB_OHCI2_CINFIG;		// External Option
+	sb_config->USBMODE.UsbMode.Ehci2				= INCHIP_USB_EHCI2_CINFIG;		// Internal Option*
+	sb_config->USBMODE.UsbMode.Ohci3				= INCHIP_USB_OHCI3_CINFIG;		// External Option
+	sb_config->USBMODE.UsbMode.Ehci3				= INCHIP_USB_EHCI3_CINFIG;		// Internal Option*
+	sb_config->USBMODE.UsbMode.Ohci4				= INCHIP_USB_OHCI4_CINFIG;		// External Option
+	// GEC
+	sb_config->GecConfig							= INCHIP_GEC_CONTROLLER;		// External Option
+	sb_config->IrConfig								= SB_IR_CONTROLLER;				// External Option
+	sb_config->XhciSwitch							= SB_XHCI_SWITCH;				// External Option
+	// Azalia
+	sb_config->AzaliaController						= INCHIP_AZALIA_CONTROLLER;		// External Option
+	sb_config->AzaliaPinCfg							= INCHIP_AZALIA_PIN_CONFIG;		// Board Level
+	sb_config->FrontPanelDetected					= INCHIP_FRONT_PANEL_DETECTED;	// Board Level
+	sb_config->AZALIACONFIG.AzaliaSdinPin			= AZALIA_PIN_CONFIG;			// Board Level
+	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr		= NULL;							// Board Level
+	sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr	= NULL;							// Board Level
+	sb_config->AnyHT200MhzLink						= INCHIP_ANY_HT_200MHZ_LINK;	// Internal Option
+	sb_config->HpetTimer							= SB_HPET_TIMER;				// External Option
+	sb_config->AzaliaSnoop							= INCHIP_AZALIA_SNOOP;			// Internal Option*
+	// Generic
+	sb_config->NativePcieSupport					= INCHIP_NATIVE_PCIE_SUPPOORT;	// External Option
+	// USB
+	sb_config->UsbPhyPowerDown						= INCHIP_USB_PHY_POWER_DOWN;	// External Option
+	sb_config->PcibClkStopOverride					= INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
+	// sb_config->HpetMsiDis							= 0;								// Field Retired
+	// sb_config->ResetCpuOnSyncFlood					= 0;								// Field Retired
+	// sb_config->PcibAutoClkCtr						= 0;								// Field Retired
+	sb_config->OEMPROGTBL.OemProgrammingTablePtr	= NULL;							// Board Level
+	sb_config->PORTCONFIG[0].PortCfg.PortPresent	= SB_GPP_PORT0;					// Board Level
+	sb_config->PORTCONFIG[0].PortCfg.PortDetected	= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[0].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[0].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
+	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
+	sb_config->PORTCONFIG[1].PortCfg.PortPresent	= SB_GPP_PORT1;					// Board Level
+	sb_config->PORTCONFIG[1].PortCfg.PortDetected	= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[1].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[1].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
+	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
+	sb_config->PORTCONFIG[2].PortCfg.PortPresent	= SB_GPP_PORT2;					// Board Level
+	sb_config->PORTCONFIG[2].PortCfg.PortDetected	= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[2].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[2].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
+	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
+	sb_config->PORTCONFIG[3].PortCfg.PortPresent	= SB_GPP_PORT3;					// Board Level
+	sb_config->PORTCONFIG[3].PortCfg.PortDetected	= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[3].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
+	sb_config->PORTCONFIG[3].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
+	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
+	sb_config->GppLinkConfig						= INCHIP_GPP_LINK_CONFIG;		// External Option
+	sb_config->GppFoundGfxDev						= 0;							// CIMx Internal Used
+	sb_config->GppFunctionEnable					= SB_GPP_CONTROLLER;			// External Option
+	sb_config->GppUnhidePorts						= INCHIP_GPP_UNHIDE_PORTS;		// Internal Option
+	sb_config->GppPortAspm							= INCHIP_GPP_PORT_ASPM;			// Internal Option
+	sb_config->GppLaneReversal						= INCHIP_GPP_LANEREVERSAL;		// External Option
+	sb_config->AlinkPhyPllPowerDown					= INCHIP_ALINK_PHY_PLL_POWER_DOWN;	// External Option
+	sb_config->GppPhyPllPowerDown					= INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
+	sb_config->GppDynamicPowerSaving				= INCHIP_GPP_DYNAMIC_POWER_SAVING;	// External Option
+	sb_config->PcieAER								= INCHIP_PCIE_AER;				// External Option
+	sb_config->PcieRAS								= INCHIP_PCIE_RAS;				// External Option
+	sb_config->GppHardwareDowngrade					= INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
+	sb_config->GppToggleReset						= INCHIP_GPP_TOGGLE_RESET;		// External Option
+	sb_config->sdbEnable							= 0;							// CIMx Internal Used
+	sb_config->TempMMIO								= NULL;							// CIMx Internal Used
+	// sb_config->GecPhyStatus							= INCHIP_GEC_PHY_STATUS;		// Field Retired
+	sb_config->SBGecPwr								= INCHIP_GEC_POWER_POLICY;		// Internal Option
+	sb_config->SBGecDebugBus						= INCHIP_GEC_DEBUGBUS;			// Internal Option
+	sb_config->SbPcieOrderRule						= INCHIP_SB_PCIE_ORDER_RULE;	// External Option
+	sb_config->AcDcMsg								= INCHIP_ACDC_MSG;				// Internal Option
+	sb_config->TimerTickTrack						= INCHIP_TIMER_TICK_TRACK;		// Internal Option
+	sb_config->ClockInterruptTag					= INCHIP_CLOCK_INTERRUPT_TAG;	// Internal Option
+	sb_config->OhciTrafficHanding					= INCHIP_OHCI_TRAFFIC_HANDING;	// Internal Option
+	sb_config->EhciTrafficHanding					= INCHIP_EHCI_TRAFFIC_HANDING;	// Internal Option
+	sb_config->FusionMsgCMultiCore					= INCHIP_FUSION_MSGC_MULTICORE;	// Internal Option
+	sb_config->FusionMsgCStage						= INCHIP_FUSION_MSGC_STAGE;		// Internal Option
+	sb_config->ALinkClkGateOff						= INCHIP_ALINK_CLK_GATE_OFF;	// External Option
+	sb_config->BLinkClkGateOff						= INCHIP_BLINK_CLK_GATE_OFF;	// External Option
+	// sb_config->sdb									= 0;								// Field Retired
+	sb_config->GppGen2Strap							= 0;							// CIMx Internal Used
+	sb_config->SlowSpeedABlinkClock					= INCHIP_SLOW_SPEED_ABLINK_CLOCK;	// Internal Option
+	sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr	= NULL;						// Board Level
+	sb_config->AbClockGating						= INCHIP_AB_CLOCK_GATING;		// External Option
+	sb_config->GppClockGating						= INCHIP_GPP_CLOCK_GATING;		// External Option
+	sb_config->L1TimerOverwrite						= INCHIP_L1_TIMER_OVERWRITE;	// Internal Option
+	// sb_config->UmiLinkWidth							= 0;								// Field Retired
+	sb_config->UmiDynamicSpeedChange				= INCHIP_UMI_DYNAMIC_SPEED_CHANGE;	// Internal Option
+	// sb_config->PcieRefClockOverclocking				= 0;								// Field Retired
+	sb_config->SbAlinkGppTxDriverStrength			= INCHIP_ALINK_GPP_TX_DRV_STRENGTH;	// Internal Option
+	sb_config->PwrFailShadow						= 0x02;							// Board Level
+	sb_config->StressResetMode						= INCHIP_STRESS_RESET_MODE;		// Internal Option
+	sb_config->hwm.fanSampleFreqDiv					= 0x03;							// Board Level
+	sb_config->hwm.hwmSbtsiAutoPoll					= 1;							// Board Level
+
+	/* General */
+	sb_config->PciClks								= SB_PCI_CLOCK_RESERVED;
+	sb_config->hwm.hwmEnable						= 0x0;
+
+#ifndef __PRE_RAM__
+	/* ramstage cimx config here */
+	if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+		sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
+	}
+
+	//sb_config->
+#endif //!__PRE_RAM__
+    printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
+}
+
+void SbPowerOnInit_Config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+        printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+		return;
+	}
+    printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
+	memset(sb_config, 0, sizeof(AMDSBCFG));
+
+    // Set the build parameters
+	sb_config->BuildParameters.BiosSize				= BIOS_SIZE;					// Field Retired
+	sb_config->BuildParameters.LegacyFree			= SBCIMx_LEGACY_FREE;			// Board Level
+	sb_config->BuildParameters.SpiSpeed				= SBCIMX_SPI_SPEED;				// Internal Option
+	sb_config->BuildParameters.SpiFastSpeed			= SBCIMX_SPI_FASTSPEED;			// Internal Option
+	// sb_config->BuildParameters.SpiWriteSpeed			=  0;							// Field Retired
+	sb_config->BuildParameters.SpiMode				= SBCIMX_SPI_MODE;				// Internal Option
+	sb_config->BuildParameters.SpiBurstWrite		= SBCIMX_SPI_BURST_WRITE;		// Internla Option
+	sb_config->BuildParameters.EcKbd				= INCHIP_EC_KBD;				// Board Level
+	sb_config->BuildParameters.Smbus0BaseAddress	= SMBUS0_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.Smbus1BaseAddress	= SMBUS1_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.SioPmeBaseAddress	= SIO_PME_BASE_ADDRESS;			// Board Level
+	sb_config->BuildParameters.WatchDogTimerBase	= WATCHDOG_TIMER_BASE_ADDRESS;	// Board Level
+	sb_config->BuildParameters.GecShadowRomBase		= GEC_ROM_SHADOW_ADDRESS;		// Board Level
+	sb_config->BuildParameters.SpiRomBaseAddress	= SPI_BASE_ADDRESS;				// Board Level
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr	= PM1_EVT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr	= PM1_CNT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr		= PM1_TMR_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.CpuControlBlkAddr	= CPU_CNT_BLK_ADDRESS;			// Board Level
+	sb_config->BuildParameters.AcpiGpe0BlkAddr		= GPE0_BLK_ADDRESS;				// Board Level
+	sb_config->BuildParameters.SmiCmdPortAddr		= SMI_CMD_PORT;					// Board Level
+	sb_config->BuildParameters.AcpiPmaCntBlkAddr	= ACPI_PMA_CNT_BLK_ADDRESS;		// Board Level
+    sb_config->SATAMODE.SataMode.SataController		= INCHIP_SATA_CONTROLLER;		// External Option
+    sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt	= SATA_COMBINE_MODE_CHANNEL;// External Option
+    sb_config->SATAMODE.SataMode.SataSetMaxGen2		= SATA_MAX_GEN2_MODE;			// External Option
+    sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE;			// External Option
+    sb_config->SATAMODE.SataMode.SataClkMode		= SATA_CLK_RESERVED;			// Internal Option
+    sb_config->NbSbGen2								= NB_SB_GEN2;					// External Option
+    sb_config->SataInternal100Spread				= INCHIP_SATA_INTERNAL_100_SPREAD;	// External Option
+    sb_config->OEMPROGTBL.OemProgrammingTablePtr	= NULL;							// Board Level
+    sb_config->sdbEnable							= 0;							// CIMx Internal Used
+    sb_config->Cg2Pll								= INCHIP_CG2_PLL;				// Internal Option
+
+    printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
+}
+
+

src/mainboard/amd/torpedo/chip.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};

src/mainboard/amd/torpedo/cmos.layout

@@ -0,0 +1,118 @@
+#*****************************************************************************
+# 
+#  This file is part of the coreboot project.
+# 
+#  Copyright (C) 2011 Advanced Micro Devices, Inc.
+# 
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+# 
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+# 
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+

src/mainboard/amd/torpedo/devicetree.cb

@@ -0,0 +1,90 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+chip northbridge/amd/agesa/family12/root_complex
+        device lapic_cluster 0 on
+                chip cpu/amd/agesa/family12
+                  device lapic 0 on end
+                end
+        end
+        device pci_domain 0 on
+                subsystemid 0x1022 0x1705 inherit
+                chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+                                chip northbridge/amd/agesa/family12 # PCI side of HT root complex
+                                        device pci 0.0 on end # Root Complex
+                                        device pci 1.0 on end # Internal Graphics Bridge
+                                        device pci 1.1 on end # Audio Controller
+                                        device pci 2.0 on end # Root Port
+                                        device pci 3.0 on end # Root Port
+                                        device pci 4.0 on end # PCIE P2P bridge
+                                        device pci 5.0 on end # PCIE P2P bridge
+                                        device pci 6.0 on end # PCIE P2P bridge
+                                        device pci 7.0 on end # PCIE P2P bridge
+                                        device pci 8.0 on end # NB/SB Link P2P bridge
+                                end # agesa northbridge
+                                chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
+                                        device pci 10.0 on end # USB XHCI
+                                        device pci 10.1 on end # USB XHCI
+                                        device pci 11.0 on end # SATA
+                                        device pci 12.0 on end # USB
+                                        device pci 12.2 on end # USB
+                                        device pci 13.0 on end # USB
+                                        device pci 13.2 on end # USB
+                                        device pci 14.0 on # SM
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end
+                                        end # SM
+                                        device pci 14.1 on end # IDE
+                                        device pci 14.2 on end # HDA
+                                        device pci 14.3 on # LPC
+												chip superio/smsc/kbc1100
+                                                        device pnp 2e.7 on #  Keyboard
+                                                                io 0x60 = 0x60
+                                                                io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                                irq 0x72 = 12
+                                                        end
+                                                end # kbc1100
+										end #LPC
+					device pci 14.4 on end # PCI bridge
+	  				device pci 14.5 on end # USB 2
+					device pci 14.6 on end # Ethernet Controller
+					device pci 14.7 on end # SD Flash Controller
+					device pci 15.0 on end # PCIe PortA
+					device pci 15.1 on end # PCIe PortB
+					device pci 15.2 on end # PCIe PortC
+					device pci 15.3 on end # PCIe PortD
+					register "gpp_configuration" = "4" #1:1:1:1
+		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/cimx/sb900
+                        device pci 18.0 on end
+                        device pci 18.1 on end
+                        device pci 18.2 on end
+                        device pci 18.3 on end
+                        device pci 18.4 on end
+                        device pci 18.5 on end
+                        device pci 18.6 on end
+                        device pci 18.7 on end
+                end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+        end #pci_domain
+end #northbridge/amd/agesa/family12/root_complex
+

src/mainboard/amd/torpedo/dimmSpd.c

@@ -0,0 +1,241 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define SMBUS_BASE_ADDR  0xB00
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct _DIMM_INFO_SMBUS{
+  UINT8   SocketId;
+  UINT8   MemChannelId;
+  UINT8   DimmId;
+  UINT8   SmbusAddress;
+} DIMM_INFO_SMBUS;
+/*
+* SPD address table - porting required
+*/
+STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] =
+{
+  /* Socket, Channel, Dimm, Smbus */
+  {0, 0, 0, 0xA0},
+  {0, 1, 0, 0xA2}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+STATIC
+VOID
+WritePmReg (
+  IN UINT8 Reg,
+  IN UINT8 Data
+  )
+{
+   __outbyte (0xCD6, Reg);
+   __outbyte (0xCD7, Data);
+}
+STATIC
+VOID
+SetupFch (
+  IN UINT16
+  IN IoBase
+  )
+{
+   WritePmReg (0x2D, IoBase >> 8);
+   WritePmReg (0x2C, IoBase | 1);
+   WritePmReg (0x29, 0x80);
+   WritePmReg (0x28, 0x61);
+   /* set SMBus clock to 400 KHz */
+   __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
+}
+
+/*
+ *
+ * ReadSmbusByteData - read a single SPD byte from any offset
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByteData (
+  IN UINT16 Iobase,
+  IN UINT8  Address,
+  OUT UINT8 *Buffer,
+  IN UINTN  Offset
+  )
+{
+   UINTN  Status;
+   UINT64 Limit;
+
+   Address |= 1; // set read bit
+
+   __outbyte (Iobase + 0, 0xFF);                // clear error status
+   __outbyte (Iobase + 1, 0x1F);                // clear error status
+   __outbyte (Iobase + 3, Offset);              // offset in eeprom
+   __outbyte (Iobase + 4, Address);             // slave address and read bit
+   __outbyte (Iobase + 2, 0x48);                // read byte command
+
+   /* time limit to avoid hanging for unexpected error status (should never happen) */
+   Limit = __rdtsc () + 2000000000 / 10;
+   for (;;) {
+     Status = __inbyte (Iobase);
+     if (__rdtsc () > Limit) break;
+     if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+     if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
+     break;
+   }
+
+   Buffer [0] = __inbyte (Iobase + 5);
+   if (Status == 2) Status = 0;                      // check for done with no errors
+   return Status;
+   }
+
+/*
+ *
+ * ReadSmbusByte - read a single SPD byte from the default offset
+ *                 this function is faster function readSmbusByteData
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByte (
+  IN UINT16 Iobase,
+  IN UINT8  Address,
+  OUT UINT8 *Buffer
+  )
+{
+  UINTN   Status;
+  UINT64  Limit;
+
+  __outbyte (Iobase + 0, 0xFF);                // clear error status
+  __outbyte (Iobase + 2, 0x44);                // read command
+
+  // time limit to avoid hanging for unexpected error status
+  Limit = __rdtsc () + 2000000000 / 10;
+  for (;;) {
+    Status = __inbyte (Iobase);
+    if (__rdtsc () > Limit) break;
+    if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+    if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
+    break;
+  }
+
+  Buffer [0] = __inbyte (Iobase + 5);
+  if (Status == 2) Status = 0;                      // check for done with no errors
+  return Status;
+}
+
+/*
+ *
+ * ReadSpd - Read one or more SPD bytes from a DIMM.
+ *           Start with offset zero and read sequentially.
+ *           Optimization relies on autoincrement to avoid
+ *           sending offset for every byte.
+ *           Reads 128 bytes in 7-8 ms at 400 KHz.
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSpd (
+  IN UINT16 IoBase,
+  IN UINT8  SmbusSlaveAddress,
+  OUT UINT8 *Buffer,
+  IN UINTN  Count
+  )
+{
+  UINTN Index, Status;
+
+  /* read the first byte using offset zero */
+  Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
+  if (Status) return Status;
+
+  /* read the remaining bytes using auto-increment for speed */
+  for (Index = 1; Index < Count; Index++){
+    Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
+    if (Status) return Status;
+  }
+  return 0;
+}
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+  IN UINT32 Func,
+  IN UINT32 Data,
+  IN OUT AGESA_READ_SPD_PARAMS *SpdData
+  )
+{
+   UINT8  SmBusAddress = 0;
+   UINTN  Index;
+   UINTN  MaxSocket = DIMENSION (SpdAddrLookup);
+   for (Index = 0; Index < MaxSocket; Index ++){
+     if ((SpdData->SocketId     == SpdAddrLookup[Index].SocketId)     &&
+         (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) &&
+         (SpdData->DimmId       == SpdAddrLookup[Index].DimmId)) {
+        SmBusAddress = SpdAddrLookup[Index].SmbusAddress;
+        break;
+      }
+   }
+
+
+   if (SmBusAddress == 0) return AGESA_ERROR;
+   SetupFch (SMBUS_BASE_ADDR);
+   return ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 128);
+}

src/mainboard/amd/torpedo/dimmSpd.h

@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+  IN UINT32 Func,
+  IN UINT32 Data,
+  IN OUT AGESA_READ_SPD_PARAMS *SpdData
+  );
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif

src/mainboard/amd/torpedo/fadt.c

@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+//#include "../../../southbridge/amd/sb900/sb900.h"
+
+/*extern*/ u16 pm_base = 0x800;
+/* pm_base should be set in sb acpi */
+/* pm_base should be got from bar2 of sb900. Here I compact ACPI
+ * registers into 32 bytes limit.
+ * */
+
+#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
+#define ACPI_PM2_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK		(pm_base + 0x08) /* 4 bytes */
+#define ACPI_GPE0_BLK		(pm_base + 0x20) /* 8 bytes */
+#define ACPI_CPU_CONTORL	(pm_base + 0x10) /* 6 bytes */
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	pm_base &= 0xFFFF;
+	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, OEM_ID, 6);
+  memcpy(header->oem_table_id, "AMD     ", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
+	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
+	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
+	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
+	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
+	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
+	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
+	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+
+	/* CpuControl is in \_PR.CPU0, 6 bytes */
+	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
+	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
+
+	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
+	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
+
+	pm_iowrite(0x6E, ACPI_PM2_CNT_BLK & 0xFF);
+	pm_iowrite(0x6F, ACPI_PM2_CNT_BLK >> 8);
+
+	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
+					* the contents of the PM registers at
+					* index 60-6B to decode ACPI I/O address.
+					* AcpiSmiEn & SmiCmdEn*/
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
+	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PM2_CNT_BLK;
+	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PM2_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}

src/mainboard/amd/torpedo/get_bus_conf.c

@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam12.h>
+#include "agesawrapper.h"
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_isa;
+u8 bus_sb900[3];
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+  0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+  0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sb900;
+
+//KZ [092110]extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+
+
+
+void get_bus_conf(void)
+{
+  u32 status;
+
+  device_t dev;
+  int i, j;
+
+  if (get_bus_conf_done == 1)
+    return;   /* do it only once */
+
+  get_bus_conf_done = 1;
+
+  printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+/*
+ * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are 
+ * written into RAM.  The routine that is responsible for writing the tables is 
+ * "write_tables", called near the end of "hardwaremain".  There is no platform 
+ * specific entry point between the S3 resume decision point and the call to 
+ * "write_tables", and the next platform specific entry points are the calls to 
+ * the ACPI table write functions.  The first of ose would seem to be the right 
+ * place, but other table write functions, e.g. the PIRQ table write function, are 
+ * called before the ACPI tables are written.  This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+  status = agesawrapper_amdinitlate(); 
+  if(status) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
+  
+  sbdn_sb900 = 0;
+
+  for (i = 0; i < 3; i++) {
+    bus_sb900[i] = 0;
+  }
+
+  for (i = 0; i < 256; i++) {
+    bus_type[i] = 0; /* default ISA bus. */
+  }
+
+
+  bus_type[0] = 1;  /* pci */
+
+//  bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+  bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
+
+  /* sb900 */
+  dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4));
+
+
+
+  if (dev) {
+    bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+    bus_isa++;
+    for (j = bus_sb900[1]; j < bus_isa; j++)
+      bus_type[j] = 1;
+  }
+
+  for (i = 0; i < 4; i++) {
+    dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, i));
+    if (dev) {
+      bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+      bus_isa++;
+    }
+  }
+  for (j = bus_sb900[2]; j < bus_isa; j++)
+    bus_type[j] = 1;
+
+
+  /* I/O APICs:   APIC ID Version State   Address */
+  bus_isa = 10;
+
+  sb_Late_Post();
+  printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+}

src/mainboard/amd/torpedo/gpio.c

@@ -0,0 +1,482 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+ 
+#include "Filecode.h"
+#include "Hudson-2.h"
+#include "AmdSbLib.h"
+#include "gpio.h"
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01   1
+#endif
+
+#ifndef SB_GPIO_REG07
+#define SB_GPIO_REG07   7
+#endif
+
+#ifndef SB_GPIO_REG25
+#define SB_GPIO_REG25   25
+#endif
+
+#ifndef SB_GPIO_REG26
+#define SB_GPIO_REG26   26
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27   27
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+	void gpioEarlyInit (void);
+ 
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+ 
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+void
+gpioEarlyInit(
+  void
+  )
+{
+	u8  Flags;
+	u8	Data8 = 0;
+	u8	StripInfo = 0;
+	u8	BoardType = 1;
+	u8	RegIndex8 = 0;
+	u8	boardRevC = 0x2;
+	u16	Data16 = 0;
+	u32	Index = 0;
+	u32	AcpiMmioAddr = 0;
+	u32	GpioMmioAddr = 0;
+	u32	IoMuxMmioAddr = 0;
+	u32	MiscMmioAddr = 0;
+    u32	SmiMmioAddr = 0;
+    u32	andMask32 = 0;
+
+	// Enable HUDSON MMIO Base (AcpiMmioAddr)
+	ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+	Data8 |= BIT0;
+	WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+	// Get HUDSON MMIO Base (AcpiMmioAddr)
+	ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);  
+	Data16 = Data8 << 8;
+	ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
+	Data16 |= Data8;
+	AcpiMmioAddr = (u32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
+	MiscMmioAddr =  AcpiMmioAddr + MISC_BASE;
+	Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
+	if ((Data8 & BIT4) == 0) {
+		BoardType = 0; // external clock board
+	}
+	Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
+	StripInfo = (Data8 & BIT7) >> 7;
+	Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
+	StripInfo |= (Data8 & BIT7) >> 6;	  
+	if (StripInfo < boardRevC) { 		// for old board. Rev B 
+		Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);		// function 3
+		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0	 
+	}
+	for (Index = 0; Index < MAX_GPIO_NO; Index++) {
+		if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
+			if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {  
+				// Configure multi-funtion
+				Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
+			}
+			// Configure GPIO
+            if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
+                Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
+                Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
+			}
+			if (Index == GPIO_65) {
+				if ( BoardType == 0 ) {
+					Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3);		// function 3
+				}
+			}
+		}
+		// Configure GEVENT
+		if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
+			SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
+    
+			andMask32 = ~(1 << (Index - GEVENT_00));
+
+			//EventEnable: 0-Disable, 1-Enable
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
+
+			//SciTrig: 0-Falling Edge, 1-Rising Edge
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
+
+			//SciLevl: 0-Edge trigger, 1-Level Trigger
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
+
+			//SmiSciEn: 0-Not send SMI, 1-Send SMI
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
+
+			//SciS0En: 0-Disable, 1-Enable
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
+
+			//SciMap: 00000b ~ 11111b
+			RegIndex8=(u8)((Index - GEVENT_00) >> 2);
+			Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));        
+      
+			//SmiTrig: 0-Active Low, 1-Active High
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
+    
+			//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 
+			RegIndex8=(u8)((Index - GEVENT_00) >> 4);
+			Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
+		}
+	}
+
+	//
+	// config MXM
+	//	GPIO9: Input for MXM_PRESENT2#
+	//	GPIO10: Input for MXM_PRESENT1#
+	//	GPIO28: Input for MXM_PWRGD
+	//	GPIO35: Output for MXM Reset
+	//	GPIO45: Output for MXM Power Enable, active HIGH
+	//	GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
+	//	GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
+	//	
+		// set INTE#/GPIO32 as GPO for PCIE_SW
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
+
+		// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0);       // GPO
+
+		// set AD9/GPIO9 as GPI for MXM_PRESENT2#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5);    // GPI
+
+		// set AD10/GPIO10 as GPI for MXM_PRESENT1#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5);    // GPI
+
+		// set GNT1#/GPIO44 as GPO for MXM Reset
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0);       // GPO
+
+		// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0);       // GPO
+
+		// set AD28/GPIO28 as GPI for MXM_PWRGD
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
+
+		// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
+
+		//
+		// [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
+		//
+		//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
+		//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
+
+		// check if there any GFX card		
+		Flags = 0;
+		// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
+		// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
+		ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
+		if (!(Data8 & BIT7))
+		{
+			//Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
+			ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
+			if (!(Data8 & BIT7))
+			{
+				Flags = 1;
+			}
+		}
+		if (  Flags )
+		{
+			// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
+			RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
+
+			// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);	
+		    
+			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)	
+			SbStall (10000);
+
+			// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
+			RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);	
+
+			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+			// WAIT POWER READY: GPIO28 (MXM_PWRGD)
+			//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
+			ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+			while (!(Data8 && BIT7))
+			{
+				ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+			}
+			// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
+		    //	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);	
+		}
+		else
+		{
+			// Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
+			RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
+
+			//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+			SbStall (10000);
+	
+			// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
+			RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); 			  						
+		}
+
+	//
+	// APU GPP0: On board LAN
+	//	GPIO25: PCIE_RST#_LAN, LOW active
+	//	GPIO63: LAN_CLKREQ#
+	//	GPIO197: LOM_POWER, HIGH Active
+	//	Clock: GPP_CLK3
+	//
+		// Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2);         // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0);          // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+		// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: 
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3);        // pullup DISABLE
+
+
+		// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
+		RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
+		
+	//
+	// APU GPP1: WUSB
+	//	GPIO1: MPCIE_RST2#, LOW active
+	//	GPIO13: WU_DISABLE#, LOW active
+	//	GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
+	//
+		// Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2);     // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // output LOW
+		RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
+
+		// Setup AD01/GPIO01 as GPO for MPCIE_RST2#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1);      // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0);       // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6);    // output LOW
+		RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+		// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
+//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1);      // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0);       // GPO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6);    // output HIGH
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+	//
+	// APU GPP2: WWAN
+	//	GPIO0: MPCIE_RST1#, LOW active
+	//	GPIO14: WP_DISABLE#, LOW active
+	//	GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
+	//
+		// Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1);     // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // output LOW
+		RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
+
+		// Set AD00/GPIO00 as GPO for MPCIE_RST1#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1);      // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0);       // GPO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6);    // output LOW
+		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+		// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
+//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1);      // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0);       // GPO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
+
+	//
+	// APU GPP3: 1394
+	//	GPIO59: Power control, HIGH active
+	//	GPIO27: PCIE_RST#_1394, LOW active
+	//	GPIO41: CLKREQ#
+	//	Clock: GPP_CLK8
+	//
+		// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: 
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+		// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1);         // GPIO
+//		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0);          // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);       // output HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+		// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1);         // CLK_REQ2#
+
+		// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
+		RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1);        // GPIO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0);         // GPO
+		RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6);       // output HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+	//  To fix glitch issue
+		RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
+	//
+	// Enable/Disable OnBoard LAN
+	//
+		if (!CONFIG_ONBOARD_LAN)
+		{ // 1 - DISABLED
+			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
+			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);	
+			RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED	
+			RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
+		}
+//		else
+//		{ // 0 - AUTO
+//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
+//		}
+
+
+	//
+	// Enable/Disable 1394
+	//
+		if (!CONFIG_ONBOARD_1394)
+		{ // 1 - DISABLED
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
+			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0);       // 1394 power off
+			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
+			RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3);    // pullup DISABLE
+			RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0);       // DISABLE GPP_CLK8
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6);   // set GPIO_GATE_C to HIGH
+		}
+//		else
+//		{ // 0 - AUTO
+//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); 
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
+//
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
+//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);	
+//		}
+
+//
+// external USB 3.0 control:
+//    amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
+//                      GPIO26: PCIE_RST#_USB3.0
+//                      GPIO46: PCIE_USB30_CLKREQ#
+//                     GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
+//                       Clock: GPP_CLK7
+//                     GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+//	if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
+// disable Onboard NEC USB3.0 controller
+		if (!CONFIG_ONBOARD_USB30) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
+		RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7 	
+		RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+		}
+//	}
+
+//
+// BlueTooth control: BT_ON
+//    amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
+//          GPIO07: BT_ON, 0 - OFF, 1 - ON
+//
+if (!CONFIG_ONBOARD_BLUETOOTH) {
+//-	if (SystemConfiguration.amdBlueTooth == 1) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
+//-	}
+}
+
+//
+// WebCam control: 
+//    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
+//       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
+//
+if (!CONFIG_ONBOARD_WEBCAM) {
+//-	if (SystemConfiguration.amdWebCam == 1) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
+//-	}  
+}
+
+//
+// Travis enable: 
+//    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
+//           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
+//
+if (!CONFIG_ONBOARD_TRAVIS) {
+//-	if (SystemConfiguration.amdTravisCtrl == 0) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
+//-	} 
+}
+
+//
+// Disable Light Sensor if needed
+//
+if (CONFIG_ONBOARD_LIGHTSENSOR) {
+//-    if (SystemConfiguration.amdLightSensor == 1) {
+        RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
+//-    }
+}
+
+}
+
+

src/mainboard/amd/torpedo/irq_tables.c

@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+//#include <cpu/amd/amdfam10_sysconf.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sb900[2];
+extern unsigned long sbdn_sb900;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb900[0];
+	pirq->rtr_devfn = ((sbdn_sb900 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb900[0], ((sbdn_sb900 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+
+
+
+	slot_num++;
+
+
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+
+}

src/mainboard/amd/torpedo/mainboard.c

@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+//#include <southbridge/amd/sb900/sb900.h>
+#include "chip.h"
+
+#define ONE_MB  0x100000
+//#define SMBUS_IO_BASE 0x6000
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void)
+{
+}
+
+/**
+ * TODO
+ * mainboard specific SB CIMx callback
+ */
+void set_pcie_dereset(void)
+{
+}
+
+uint64_t uma_memory_base, uma_memory_size;
+
+/*************************************************
+* enable the dedicated function in torpedo board.
+*************************************************/
+static void torpedo_enable(device_t dev)
+{
+  printk(BIOS_INFO, "Mainboard Torpedo Enable. dev=0x%p\n", dev);
+#if (CONFIG_GFXUMA == 1)
+  msr_t msr, msr2;
+  uint32_t sys_mem;
+
+  /* TOP_MEM: the top of DRAM below 4G */
+  msr = rdmsr(TOP_MEM);
+  printk
+      (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+       __func__, msr.lo, msr.hi);
+
+  /* TOP_MEM2: the top of DRAM above 4G */
+  msr2 = rdmsr(TOP_MEM2);
+  printk
+      (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+       __func__, msr2.lo, msr2.hi);
+
+  /* refer to UMA Size Consideration in Family12h BKDG. */
+  /* Please reference MemNGetUmaSizeLN () */
+  /*
+   *     Total system memory   UMASize
+   *     >= 2G                 512M
+   *     >=1G                  256M
+   *     <1G                    64M
+   */
+  sys_mem = msr.lo;
+  sys_mem = msr.lo + 16 * ONE_MB;   // Ignore 16MB allocated for C6 when finding UMA size
+  if (sys_mem >= 2048 * ONE_MB) {
+    uma_memory_size = 512 * ONE_MB;
+  } else if (sys_mem >= 1024 * ONE_MB) {
+    uma_memory_size = 256 * ONE_MB;
+  } else {
+    uma_memory_size = 64 * ONE_MB;
+  }
+  uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+  printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+        __func__, uma_memory_size, uma_memory_base);
+
+  /* TODO: TOP_MEM2 */
+#else
+  uma_memory_size = 0x10000000; /* 256M recommended UMA */
+  uma_memory_base = 0x30000000; /* 1GB  system memory supported */
+#endif
+
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+  /* UMA is removed from system memory in the northbridge code, but
+   * in some circumstances we want the memory mentioned as reserved.
+   */
+#if (CONFIG_GFXUMA == 1)
+  printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+        uma_memory_base, uma_memory_size);
+  lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+          uma_memory_size);
+#endif
+  return 0;
+}
+struct chip_operations mainboard_ops = {
+  CHIP_NAME("AMD TORPEDO Mainboard")
+  .enable_dev = torpedo_enable,
+};

src/mainboard/amd/torpedo/mptable.c

@@ -0,0 +1,252 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+
+//-#define IO_APIC_ID    CONFIG_MAX_PHYSICAL_CPUS + 1
+#define IO_APIC_ID    CONFIG_MAX_CPUS
+extern u8 bus_sb900[2];
+
+
+extern u32 bus_type[256];
+extern u32 sbdn_sb900;
+u32 apicid_sb900;
+
+u8 picr_data[] = {
+  0x0B,0x0B,0x0B,0x0B,0x1F,0x1F,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 
+  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0B,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x0B,0x0B,0x0B,0x0B
+};
+u8 intr_data[] = {
+  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 
+  0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+  mc->mpc_length += length;
+  mc->mpc_entry_count++;
+}
+static void my_smp_write_bus(struct mp_config_table *mc,
+  unsigned char id, const char *bustype)
+{
+  struct mpc_config_bus *mpc;
+  mpc = smp_next_mpc_entry(mc);
+  memset(mpc, '\0', sizeof(*mpc));
+  mpc->mpc_type = MP_BUS;
+  mpc->mpc_busid = id;
+  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+  smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+static void *smp_write_config_table(void *v)
+{
+  struct mp_config_table *mc;
+  int bus_isa;
+  int boot_apic_id;
+  unsigned apic_version;
+  unsigned cpu_features;
+  unsigned cpu_feature_flags;
+  struct cpuid_result result;
+  unsigned long cpu_flag;
+
+  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+  mptable_init(mc, LAPIC_ADDR);
+  memcpy(mc->mpc_oem, "AMD     ", 8);
+
+  /*Inagua used dure core cpu with one die */
+  boot_apic_id = lapicid();
+  apic_version = lapic_read(LAPIC_LVR) & 0xff;
+  result = cpuid(1);
+  cpu_features = result.eax;
+  cpu_feature_flags = result.edx;
+  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
+  smp_write_processor(mc,
+      0, apic_version,
+      cpu_flag, cpu_features, cpu_feature_flags
+    );
+  
+  cpu_flag = MPC_CPU_ENABLED;
+  smp_write_processor(mc,
+      1, apic_version,
+      cpu_flag, cpu_features, cpu_feature_flags
+    );
+
+  get_bus_conf();
+
+  //mptable_write_buses(mc, NULL, &bus_isa);
+  my_smp_write_bus(mc, 0, "PCI   ");
+  my_smp_write_bus(mc, 1, "PCI   ");
+  bus_isa = 0x02;
+  my_smp_write_bus(mc, bus_isa, "ISA   ");
+
+  /* I/O APICs:   APIC ID Version State   Address */
+  
+  device_t dev;
+  u32 dword;
+  u8 byte;
+    
+  dword = 0;
+  dword = pm_ioread(0x34) & 0xF0;
+  dword |= (pm_ioread(0x35) & 0xFF) << 8;
+  dword |= (pm_ioread(0x36) & 0xFF) << 16;
+  dword |= (pm_ioread(0x37) & 0xFF) << 24;
+  /* Set IO APIC ID onto IO_APIC_ID */
+  write32 (dword, 0x00);
+  write32 (dword + 0x10, IO_APIC_ID << 24);
+  apicid_sb900 = IO_APIC_ID;
+  smp_write_ioapic(mc, apicid_sb900, 0x21, dword);
+  
+  /* PIC IRQ routine */
+  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+    outb(byte, 0xC00);
+    outb(picr_data[byte], 0xC01);
+  }
+  
+  /* APIC IRQ routine */
+  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+    outb(byte | 0x80, 0xC00);
+    outb(intr_data[byte], 0xC01);
+  }
+
+    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0);
+  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb900, 0x0);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb900, 0x1);
+  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb900, 0x2);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb900, 0x3);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb900, 0x4);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb900, 0x11);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb900, 0x6);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb900, 0x7);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb900, 0x8);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb900, 0x9);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb900, 0xa);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb900, 0x13);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb900, 0xc);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb900, 0xd);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb900, 0xe);
+  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb900, 0xf);
+
+  /* PCI interrupts are level triggered, and are
+   * associated with a specific bus/device/function tuple.
+   */
+#define PCI_INT(bus, dev, int_sign, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
+
+  /* Internal VGA */
+  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+  
+  /* SMBUS */
+  PCI_INT(0x0, 0x14, 0x0, 0x10);
+  
+  /* HD Audio */
+  PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+  
+  /* USB */
+  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); 
+  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+  PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+  /* sata */
+  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+
+  /* on board NIC & Slot PCIE.  */
+  
+  /* PCI slots */
+  /* PCI_SLOT 0. */
+  PCI_INT(bus_sb900[1], 0x5, 0x0, 0x14);
+  PCI_INT(bus_sb900[1], 0x5, 0x1, 0x15);
+  PCI_INT(bus_sb900[1], 0x5, 0x2, 0x16);
+  PCI_INT(bus_sb900[1], 0x5, 0x3, 0x17);
+
+  /* PCI_SLOT 1. */
+  PCI_INT(bus_sb900[1], 0x6, 0x0, 0x15);
+  PCI_INT(bus_sb900[1], 0x6, 0x1, 0x16);
+  PCI_INT(bus_sb900[1], 0x6, 0x2, 0x17);
+  PCI_INT(bus_sb900[1], 0x6, 0x3, 0x14);
+
+  /* PCI_SLOT 2. */
+  PCI_INT(bus_sb900[1], 0x7, 0x0, 0x16);
+  PCI_INT(bus_sb900[1], 0x7, 0x1, 0x17);
+  PCI_INT(bus_sb900[1], 0x7, 0x2, 0x14);
+  PCI_INT(bus_sb900[1], 0x7, 0x3, 0x15);
+
+  PCI_INT(bus_sb900[2], 0x0, 0x0, 0x12);
+  PCI_INT(bus_sb900[2], 0x0, 0x1, 0x13);
+  PCI_INT(bus_sb900[2], 0x0, 0x2, 0x14);
+
+  /* PCIe Lan*/
+  PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+  /* FCH PCIe PortA */
+  PCI_INT(0x0, 0x15, 0x0, 0x10);
+  /* FCH PCIe PortB */
+  PCI_INT(0x0, 0x15, 0x1, 0x11);
+  /* FCH PCIe PortC */
+  PCI_INT(0x0, 0x15, 0x2, 0x12);
+  /* FCH PCIe PortD */
+  PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+  /* There is no extension information... */
+
+  /* Compute the checksums */
+  mc->mpe_checksum =
+      smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+  mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+  printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
+         mc, smp_next_mpe_entry(mc));
+  return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+  void *v;
+  v = smp_write_floating_table(addr);
+  return (unsigned long)smp_write_config_table(v);
+}

src/mainboard/amd/torpedo/pmio.c

@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>	/*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+	outb(reg, port_base);
+	outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+	outb(reg, port_base);
+	return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+	return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+	pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+	return pmio_read_index(PM2_INDEX, reg);
+}
+

src/mainboard/amd/torpedo/pmio.h

@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX	0xCD6
+#define PM_DATA		0xCD7
+#define PM2_INDEX	0xCD0
+#define PM2_DATA	0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif

src/mainboard/amd/torpedo/reset.c

@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h>		/*inb, outb*/
+#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+

src/mainboard/amd/torpedo/romstage.c

@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "agesawrapper.h"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "pc80/i8254.c"
+#include "pc80/i8259.c"
+#include "SbEarly.h"
+#include "SbPlatform.h"
+#include <arch/cpu.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+  u32 val;
+
+  post_code(0x35);
+  val = agesawrapper_amdinitmmio();
+  if(val) {
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
+
+  if (!cpu_init_detectedx && boot_cpu()) {
+    post_code(0x30);
+	gpioEarlyInit();
+    sb_poweron_init();
+
+    post_code(0x31);
+
+    kbc1100_early_init(CONFIG_SIO_PORT);
+
+    post_code(0x32);
+    uart_init();
+    post_code(0x33);
+    console_init();
+  }
+
+  /* Halt if there was a built in self test failure */
+  post_code(0x34);
+  report_bist_failure(bist);
+
+  // Load MPB
+  val = cpuid_eax(1);
+  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+  post_code(0x36);
+  val = agesawrapper_amdinitreset();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+
+  post_code(0x37);
+  val = agesawrapper_amdinitearly ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+  post_code(0x38);
+  val = agesawrapper_amdinitpost ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+  post_code(0x39);
+  sb_before_pci_init ();
+  printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+
+  post_code(0x40);
+  val = agesawrapper_amdinitenv ();
+  if(val) {
+    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+  }
+  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+  /* Initialize i8259 pic */
+  post_code(0x41);
+  setup_i8259 ();
+  printk(BIOS_DEBUG, "Got past setup_i8259\n");
+
+  /* Initialize i8254 timers */
+  post_code(0x42);
+  setup_i8254 ();
+  printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
+  post_code(0x43);
+  copy_and_run(0);
+  printk(BIOS_DEBUG, "Got past copy_and_run\n");
+
+  post_code(0x44);  // Should never see this post code.
+}
+