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Add IOAPIC support for Intel 82371EB and fixup SMP on ASUS P2B-D. 

- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
   Intel 82371EB southbridge (sets the proper chip-select) and sets an
   IOAPIC ID.

 - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
   as on 82371EB-based boards the IOAPIC is an external chip (not integrated
   in the southbridge) and it's only populated on multi-CPU boards.
   That is, we cannot unconditionally enable it, only on SMP-capable boards.

 - Due to the reason explained above, remove "select IOAPIC" from
   src/southbridge/intel/i82371eb/Kconfig, and add it to
   src/mainboard/asus/p2b-d/Kconfig.

 - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
   CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
   didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).

 - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
   that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
   are set.

 - Rework ASUS P2B-D mptable.c to fix a number of things:

   - Convert it to use mptable_write_buses() as all mptable.c files should do.

   - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).

   - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.

This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
On Linux I now get two entries in /proc/cpuinfo (where only one appeared
before this patch), i.e. both populated CPUs are found.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-10-28 08:19:22 +00:00
parent 706b350be8
commit 77180546c8
6 changed files with 69 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/asus/p2b-d/Kconfig
View File

@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
select IOAPIC
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
select SDRAMPWR_4DIMM
@ -48,4 +49,8 @@ config MAX_CPUS
int
default 2
config MAX_PHYSICAL_CPUS
int
default 2
endif # BOARD_ASUS_P2B_D

10
src/mainboard/asus/p2b-d/devicetree.cb
View File

@ -1,10 +1,10 @@
chip northbridge/intel/i440bx # Northbridge
device lapic_cluster 0 on # APIC cluster
chip cpu/intel/slot_1 # CPU
device lapic 0 on end # APIC
device lapic_cluster 0 on # (L)APIC cluster
chip cpu/intel/slot_1 # CPU socket 0
device lapic 0 on end # Local APIC of CPU 0
end
chip cpu/intel/slot_1 # CPU
device lapic 1 on end # APIC
chip cpu/intel/slot_1 # CPU socket 1
device lapic 1 on end # Local APIC of CPU 1
end
end
device pci_domain 0 on # PCI domain

42
src/mainboard/asus/p2b-d/mptable.c
View File

@ -27,6 +27,7 @@
static void *smp_write_config_table(void *v)
{
int ioapic_id, ioapic_ver, isa_bus;
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -35,13 +36,12 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
/* Bus: Bus ID Type */
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "ISA ");
mptable_write_buses(mc, NULL, &isa_bus);
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
@ -49,45 +49,39 @@ static void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 3, 0x20, res->base);
smp_write_ioapic(mc, 3, ioapic_ver, res->base);
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 4, 0x20, res->base);
smp_write_ioapic(mc, 4, ioapic_ver, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 5, 0x20, res->base);
smp_write_ioapic(mc, 5, ioapic_ver, res->base);
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
smp_write_ioapic(mc, 8, 0x20, res->base);
smp_write_ioapic(mc, 8, ioapic_ver, res->base);
}
}
mptable_add_isa_interrupts(mc, 0x2, 0x2, 0);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0x2, 0xb, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
0x2, 0xa, 0x2, 0x13);
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x2, 0x0,
MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x2, 0x0, MP_APIC_ALL, 0x1);
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
/* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);

3
src/mainboard/asus/p2b-d/romstage.c
View File

@ -25,7 +25,6 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include "southbridge/intel/i82371eb/i82371eb.h"
#include "northbridge/intel/i440bx/raminit.h"
@ -48,8 +47,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
void main(unsigned long bist)
{
enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

1
src/southbridge/intel/i82371eb/Kconfig
View File

@ -1,6 +1,5 @@
config SOUTHBRIDGE_INTEL_I82371EB
bool
select IOAPIC
select TINY_BOOTBLOCK
config BOOTBLOCK_SOUTHBRIDGE_INIT

41
src/southbridge/intel/i82371eb/i82371eb_isa.c
View File

@ -28,6 +28,35 @@
#include <arch/ioapic.h>
#include "i82371eb.h"
static void enable_intel_82093aa_ioapic(void)
{
u16 reg16;
u32 reg32;
u8 ioapic_id = 2;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
device_t dev;
dev = dev_find_device(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
/* Enable IOAPIC. */
reg16 = pci_read_config16(dev, XBCS);
reg16 |= (1 << 8); /* APIC Chip Select */
pci_write_config16(dev, XBCS, reg16);
/* Set the IOAPIC ID. */
*ioapic_index = 0;
*ioapic_data = ioapic_id << 24;
/* Read back and verify the IOAPIC ID. */
*ioapic_index = 0;
reg32 = (*ioapic_data >> 24) & 0x0f;
printk(BIOS_DEBUG, "IOAPIC ID = %x\n", reg32);
if (reg32 != ioapic_id)
die("IOAPIC error!\n");
}
static void isa_init(struct device *dev)
{
u32 reg32;
@ -45,6 +74,18 @@ static void isa_init(struct device *dev)
/* Initialize ISA DMA. */
isa_dma_init();
#if CONFIG_IOAPIC
/*
* Unlike most other southbridges the 82371EB doesn't have a built-in
* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
* have a discrete IOAPIC (Intel 82093AA) soldered onto the board.
*
* Thus, we can/must only enable the IOAPIC if it actually exists,
* i.e. the respective mainboard does "select IOAPIC".
*/
enable_intel_82093aa_ioapic();
#endif
}
static void sb_read_resources(struct device *dev)