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77180546c8
- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the Intel 82371EB southbridge (sets the proper chip-select) and sets an IOAPIC ID. - We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC" as on 82371EB-based boards the IOAPIC is an external chip (not integrated in the southbridge) and it's only populated on multi-CPU boards. That is, we cannot unconditionally enable it, only on SMP-capable boards. - Due to the reason explained above, remove "select IOAPIC" from src/southbridge/intel/i82371eb/Kconfig, and add it to src/mainboard/asus/p2b-d/Kconfig. - Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already). - Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c, that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC are set. - Rework ASUS P2B-D mptable.c to fix a number of things: - Convert it to use mptable_write_buses() as all mptable.c files should do. - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC). - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc. This is build-tested on ASUS P2B-D, and also boot-tested successfully there. On Linux I now get two entries in /proc/cpuinfo (where only one appeared before this patch), i.e. both populated CPUs are found. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS you can find in most of today's computers. It performs just a little bit of hardware initialization and then executes one of many possible payloads, e.g. a Linux kernel or a bootloader. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.