soc/intel/alderlake: add processor power limits control support
Add processor power limits control support to configure values for alderlake soc based platforms. BRANCH=None BUG=None TEST=Build and test on alderlake rvp board Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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src/soc/intel/alderlake
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@ -59,6 +59,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_COMMON_BLOCK_MEMINIT
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select SOC_INTEL_COMMON_BLOCK_MEMINIT
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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@ -7,6 +7,7 @@
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#include <intelblocks/cfg.h>
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#include <intelblocks/cfg.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/gspi.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/pcie_rp.h>
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#include <intelblocks/pcie_rp.h>
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#include <soc/gpe.h>
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#include <soc/gpe.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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@ -24,6 +25,9 @@ struct soc_intel_alderlake_config {
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/* Common struct containing soc config data required by common code */
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/* Common struct containing soc config data required by common code */
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struct soc_intel_common_config common_soc_config;
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struct soc_intel_common_config common_soc_config;
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/* Common struct containing power limits configuration information */
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struct soc_power_limits_config power_limits_config;
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/* Gpio group routed to each dword of the GPE0 block. Values are
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form PMC_GPP_[A:U] or GPD. */
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* of the form PMC_GPP_[A:U] or GPD. */
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uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
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@ -8,8 +8,11 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <delay.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/soc_chip.h>
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#include <soc/systemagent.h>
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#include <soc/systemagent.h>
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/*
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/*
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@ -48,12 +51,20 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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*/
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*/
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void soc_systemagent_init(struct device *dev)
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void soc_systemagent_init(struct device *dev)
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{
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{
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struct soc_power_limits_config *soc_config;
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config_t *config;
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/* Enable Power Aware Interrupt Routing */
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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enable_bios_reset_cpl();
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/* TODO: Add set_power_limits() */
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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config = config_of_soc();
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soc_config = &config->power_limits_config;
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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}
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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