soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
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select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
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select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
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select SOC_INTEL_COMMON_BLOCK_CAR
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CNVI
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@ -44,9 +44,6 @@
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/* PCI _OSC */
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#include <soc/intel/common/acpi/pci_osc.asl>
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/* Intel Power Engine Plug-in */
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#include <soc/intel/common/block/acpi/acpi/pep.asl>
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/* EMMC/SD card */
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#include "scs.asl"
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@ -4,6 +4,7 @@
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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@ -101,9 +102,18 @@ static void pm1_enable_pwrbtn_smi(void *unused)
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
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static void pmc_fill_ssdt(const struct device *dev)
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{
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if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
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generate_acpi_power_engine();
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}
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struct device_operations pmc_ops = {
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.read_resources = soc_pmc_read_resources,
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.set_resources = noop_set_resources,
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.init = soc_acpi_mode_init,
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.enable = pmc_init,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_fill_ssdt = pmc_fill_ssdt,
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#endif
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};
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