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mb/google/skyrim/var/winterhold: adjust the eDP panel power sequence 

set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms
between backlight on and vary backlight.

BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table;
measure the power on sequence on whiterun

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Chris.Wang 2023-03-16 15:24:02 +08:00 committed by Felix Held
parent f83b282856
commit 77c5d898ae
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
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@ -112,6 +112,9 @@ chip soc/amd/mendocino
register "dxio_tx_vboost_enable" = "1" register "dxio_tx_vboost_enable" = "1"
# The unit is set to one per 4ms
register "pwr_on_vary_bl_to_blon" = "0x1c"
device ref gpp_bridge_1 on device ref gpp_bridge_1 on
# Required so the NVMe gets placed into D3 when entering S0i3. # Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device chip drivers/pcie/rtd3/device