mb/purism/librem_cnl: convert to using overridetrees
Convert the librem_14 and librem_mini from using separate devicetrees to using a baseboard devicetree and overridetrees. This reduces code duplication, and facilitates adding any new variants with minimal additional code. Test: build/boot Librem 14 and Librem Mini v2 boards Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier
Felix Held
parent
57779955c9
commit
77c86aafeb
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@ -32,8 +32,8 @@ config VARIANT_DIR
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default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
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default "librem_14" if BOARD_PURISM_LIBREM_14
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config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config CBFS_SIZE
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default 0x800000 if BOARD_PURISM_LIBREM_MINI
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@ -0,0 +1,103 @@
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chip soc/intel/cannonlake
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_Enabled"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Acoustic Noise
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register "AcousticNoiseMitigation" = "1"
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register "FastPkgCRampDisableIa" = "1"
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register "FastPkgCRampDisableGt" = "1"
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register "FastPkgCRampDisableSa" = "1"
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register "FastPkgCRampDisableFivr" = "1"
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register "SlowSlewRateForIa" = "3" # fast/16
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register "SlowSlewRateForGt" = "3" # fast/16
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register "SlowSlewRateForSa" = "3" # fast/16
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register "SlowSlewRateForFivr" = "3" # fast/16
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "10"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHC
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on end # LPC Bridge
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device pci 1f.1 off end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -15,12 +15,6 @@ chip soc/intel/cannonlake
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.tdp_pl2_override = 20,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_Enabled"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Serial I/O
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@ -28,45 +22,8 @@ chip soc/intel/cannonlake
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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}"
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# Acoustic Noise
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register "AcousticNoiseMitigation" = "1"
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register "FastPkgCRampDisableIa" = "1"
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register "FastPkgCRampDisableGt" = "1"
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register "FastPkgCRampDisableSa" = "1"
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register "FastPkgCRampDisableFivr" = "1"
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register "SlowSlewRateForIa" = "3" # fast/16
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register "SlowSlewRateForGt" = "3" # fast/16
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register "SlowSlewRateForSa" = "3" # fast/16
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register "SlowSlewRateForFivr" = "3" # fast/16
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "10"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on # Integrated Graphics Device
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register "gfx" = "GMA_DEFAULT_PANEL(0)"
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register "panel_cfg" = "{
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@ -78,11 +35,6 @@ chip soc/intel/cannonlake
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.backlight_off_delay_ms = 1,
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}"
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end
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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chip drivers/usb/acpi
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device usb 0.0 on
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@ -189,15 +141,6 @@ chip soc/intel/cannonlake
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device i2c 2c on end
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end
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end
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "satapwroptimize" = "1"
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register "SataSalpSupport" = "1"
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@ -208,16 +151,6 @@ chip soc/intel/cannonlake
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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end
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpSlotImplemented[6]" = "1"
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@ -241,9 +174,6 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[0]" = "0"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
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register "PcieRpEnable[12]" = "1"
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register "PcieRpSlotImplemented[12]" = "1"
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@ -252,13 +182,6 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[1]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Bridge
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
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@ -271,13 +194,5 @@ chip soc/intel/cannonlake
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 off end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -7,62 +7,19 @@ chip soc/intel/cannonlake
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.tdp_pl2_override = 28,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_FixedHigh"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# Misc
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register "AcousticNoiseMitigation" = "1"
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register "FastPkgCRampDisableIa" = "1"
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register "FastPkgCRampDisableGt" = "1"
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register "FastPkgCRampDisableSa" = "1"
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register "FastPkgCRampDisableFivr" = "1"
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register "SlowSlewRateForIa" = "3" # fast/16
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register "SlowSlewRateForGt" = "3" # fast/16
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register "SlowSlewRateForSa" = "3" # fast/16
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register "SlowSlewRateForFivr" = "3" # fast/16
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "12"
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# Serial IRQ Mode
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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chip drivers/usb/acpi
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device usb 0.0 on
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@ -166,33 +123,11 @@ chip soc/intel/cannonlake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataPortsEnable[0]" = "1" # 2.5"
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register "SataPortsEnable[2]" = "1" # m.2
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register "satapwroptimize" = "1"
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end
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN)
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register "PcieRpSlotImplemented[7]" = "1"
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register "PcieRpEnable[7]" = "1"
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@ -201,15 +136,12 @@ chip soc/intel/cannonlake
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register "PcieClkSrcUsage[2]" = "0x80"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
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end
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 on # PCI Express Port 10
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device pci 00.0 on end # x1 (LAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieClkSrcUsage[3]" = "9"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
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register "PcieRpSlotImplemented[12]" = "1"
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register "PcieRpEnable[12]" = "1"
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@ -218,21 +150,5 @@ chip soc/intel/cannonlake
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register "PcieClkSrcClkReq[1]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on end # LPC Bridge
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 hidden end # Power Management Controller
|
||||
device pci 1f.3 on # Intel HDA
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
end
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
Loading…
Reference in New Issue