soc/intel/tigerlake: Update PMC Register Base and platform check for JSP

Change:
1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP
2. Platform check in espi.c

BUG=None
TEST=
	1. Test for JSL RVP Boot
	2. Verify PMC register values are valid for GEN_PMCON
	   and GBLRST_CAUSE from the coreboot console logs.


Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/bootblock/pch.c

@@ -41,7 +41,7 @@
 #include <soc/pm.h>
 
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP	0x1100
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0x0980
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP	0xA00
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8

src/soc/intel/tigerlake/espi.c

@@ -83,7 +83,7 @@ uint8_t get_pch_series(void)
 
 	if (lpc_did_hi_byte == 0xA0)
 		return PCH_TGP;
-	else if (lpc_did_hi_byte == 0x38)
+	else if (lpc_did_hi_byte == 0x4d)
 		return PCH_JSP;
 	else
 		return PCH_UNKNOWN_SERIES;