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ACPI GNVS: Drop APIC, factor out MPEN 

APIC was not referenced anywhere in ASL.

MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.

MPEN has reference also in Intel SpeedStep ASL.

Replace static MPEN with detection of multiple CPUs
installed.

Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-12-29 05:12:56 +02:00
parent c196246f75
commit 780e02d1a5
26 changed files with 30 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/acer/g43t-am3/acpi_tables.c
View File

@ -7,6 +7,4 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
gnvs->apic = 1; /* Enable APIC */
gnvs->mpen = 1; /* Enable Multi Processing */
} }

2
src/mainboard/asus/p5qc/acpi_tables.c
View File

@ -7,7 +7,5 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
gnvs->apic = 1; /* Enable APIC */
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->cmap = 0x01; /* Enable COM 1 port */ gnvs->cmap = 0x01; /* Enable COM 1 port */
} }

2
src/mainboard/asus/p5ql-em/acpi_tables.c
View File

@ -7,7 +7,5 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
gnvs->apic = 1; /* Enable APIC */
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->cmap = 0x01; /* Enable COM 1 port */ gnvs->cmap = 0x01; /* Enable COM 1 port */
} }

2
src/mainboard/emulation/qemu-q35/acpi_tables.c
View File

@ -15,8 +15,6 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
/* Enable both COM ports */ /* Enable both COM ports */
gnvs->cmap = 0x01; gnvs->cmap = 0x01;

2
src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
View File

@ -9,7 +9,5 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
gnvs->lptp = 0; /* LPT port */ gnvs->lptp = 0; /* LPT port */
gnvs->fdcp = 0; /* Floppy Disk Controller */ gnvs->fdcp = 0; /* Floppy Disk Controller */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
gnvs->apic = 1; /* Enable APIC */
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->cmap = 0x01; /* Enable COM 1 port */ gnvs->cmap = 0x01; /* Enable COM 1 port */
} }

2
src/mainboard/intel/dg43gt/acpi_tables.c
View File

@ -7,7 +7,5 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */ gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
gnvs->apic = 1; /* Enable APIC */
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->cmap = 0x01; /* Enable COM 1 port */ gnvs->cmap = 0x01; /* Enable COM 1 port */
} }

2
src/mainboard/lenovo/t400/acpi_tables.c
View File

@ -9,8 +9,6 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
/* Enable both COM ports */ /* Enable both COM ports */
gnvs->cmap = 0x01; gnvs->cmap = 0x01;

2
src/mainboard/lenovo/x200/acpi_tables.c
View File

@ -9,8 +9,6 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
/* Enable both COM ports */ /* Enable both COM ports */
gnvs->cmap = 0x01; gnvs->cmap = 0x01;

2
src/mainboard/roda/rk9/acpi_tables.c
View File

@ -9,8 +9,6 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
/* Enable both COM ports */ /* Enable both COM ports */
gnvs->cmap = 0x01; gnvs->cmap = 0x01;

4
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View File

@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

4
src/southbridge/intel/bd82x6x/include/soc/nvs.h
View File

@ -44,8 +44,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2]; u8 rsvd3[2];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

8
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -12,7 +12,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <string.h> #include <string.h>
@ -24,7 +23,6 @@
#include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h> #include <southbridge/intel/common/spi.h>
#include <soc/nvs.h>
#define NMI_OFF 0 #define NMI_OFF 0
@ -641,12 +639,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev); pch_enable(dev);
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";

2
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
View File

@ -52,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1

2
src/southbridge/intel/i82801gx/include/soc/nvs.h
View File

@ -40,7 +40,7 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3]; u8 rsvd3[3];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */

4
src/southbridge/intel/i82801gx/lpc.c
View File

@ -466,8 +466,8 @@ static void lpc_final(struct device *dev)
void soc_fill_gnvs(struct global_nvs *gnvs) void soc_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->apic = 1; /* MPEN, Enable Multi Processing. */
gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
} }
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)

2
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
View File

@ -53,7 +53,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1

2
src/southbridge/intel/i82801ix/include/soc/nvs.h
View File

@ -40,7 +40,7 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3]; u8 rsvd3[3];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */

8
src/southbridge/intel/i82801ix/lpc.c
View File

@ -12,6 +12,7 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <string.h> #include <string.h>
@ -20,6 +21,7 @@
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <soc/nvs.h>
#define NMI_OFF 0 #define NMI_OFF 0
@ -450,6 +452,12 @@ static void i82801ix_lpc_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
/* MPEN, Enable Multi Processing. */
gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";

4
src/southbridge/intel/i82801jx/acpi/globalnvs.asl
View File

@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

4
src/southbridge/intel/i82801jx/include/soc/nvs.h
View File

@ -39,8 +39,8 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3]; u8 rsvd3[3];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

4
src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
View File

@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

4
src/southbridge/intel/ibexpeak/include/soc/nvs.h
View File

@ -45,8 +45,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2]; u8 rsvd3[2];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

8
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -13,7 +13,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <elog.h> #include <elog.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <string.h> #include <string.h>
@ -23,7 +22,6 @@
#include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/spi.h> #include <southbridge/intel/common/spi.h>
#include <soc/nvs.h>
#define NMI_OFF 0 #define NMI_OFF 0
@ -541,12 +539,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev); pch_enable(dev);
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";

4
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
View File

@ -54,8 +54,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */ /* Processor Identification */
Offset (0x28), Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1 PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state PPCM, 8, // 0x2c - Max. PPC state

4
src/southbridge/intel/lynxpoint/include/soc/nvs.h
View File

@ -44,8 +44,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */ u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2]; u8 rsvd3[2];
/* Processor Identification */ /* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */ u8 ppcm; /* 0x2c - Max. PPC state */

8
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -11,7 +11,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <string.h> #include <string.h>
#include "chip.h" #include "chip.h"
@ -21,7 +20,6 @@
#include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h> #include <southbridge/intel/common/spi.h>
#include <soc/nvs.h>
#define NMI_OFF 0 #define NMI_OFF 0
@ -679,12 +677,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev); pch_enable(dev);
} }
void soc_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
}
static const char *lpc_acpi_name(const struct device *dev) static const char *lpc_acpi_name(const struct device *dev)
{ {
return "LPCB"; return "LPCB";