Separate cache_as_ram_auto.c and failover.c for Tyan s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
4e2ffb8812
commit
782de9aa5e
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@ -29,10 +29,25 @@ if CONFIG_HAVE_ACPI_TABLES
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end
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if CONFIG_USE_INIT
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if CONFIG_USE_FAILOVER_IMAGE
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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else
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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end
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else #CONFIG_USE_INIT
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if CONFIG_USE_FAILOVER_IMAGE
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/failover.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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else
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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@ -41,51 +56,32 @@ else
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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end #CONFIG_USE_INIT
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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##
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@ -97,21 +93,14 @@ ldscript /southbridge/nvidia/ck804/id.lds
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##
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## ROMSTRAP table for CK804
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##
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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##
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## Setup Cache-As-Ram
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##
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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###
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@ -119,14 +108,8 @@ end
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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ldscript /arch/i386/lib/failover_failover.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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if CONFIG_USE_FAILOVER_IMAGE
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ldscript /arch/i386/lib/failover_failover.lds
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end
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##
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@ -1,4 +1,3 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#define K8_ALLOCATE_IO_RANGE 1
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@ -21,11 +20,12 @@
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#if CONFIG_USE_FAILOVER_IMAGE==0
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#define post_code(x) outb(x, 0x80)
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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@ -34,8 +34,6 @@
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
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@ -44,8 +42,6 @@
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#define SUPERIO_GPIO_IO_BASE 0x400
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#if CONFIG_USE_FAILOVER_IMAGE==0
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/debug.c"
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@ -118,116 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/model_fxx/init_cpus.c"
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#endif
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#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
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#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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static void sio_setup(void)
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{
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unsigned value;
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uint32_t dword;
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uint8_t byte;
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
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byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1<<29)|(1<<0);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
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dword |= (1<<16);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
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lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
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value &= 0xbf;
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
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}
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void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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unsigned last_boot_normal_x = last_boot_normal();
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/* Is this a cpu only reset? or Is this a secondary cpu? */
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if ((cpu_init_detectedx) || (!boot_cpu())) {
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if (last_boot_normal_x) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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}
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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sio_setup();
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/* Setup the ck804 */
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ck804_enable_rom();
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/* Is this a deliberate reset by the bios */
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// post_code(0x22);
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if (bios_reset_detected() && last_boot_normal_x) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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normal_image:
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// post_code(0x23);
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__asm__ volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
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);
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fallback_image:
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// post_code(0x25);
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#if CONFIG_HAVE_FAILOVER_BOOT==1
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__asm__ volatile ("jmp __fallback_image"
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: /* outputs */
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: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
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)
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#endif
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;
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}
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#endif
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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#if CONFIG_HAVE_FAILOVER_BOOT==1
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#if CONFIG_USE_FAILOVER_IMAGE==1
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failover_process(bist, cpu_init_detectedx);
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#else
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real_main(bist, cpu_init_detectedx);
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#endif
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#else
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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failover_process(bist, cpu_init_detectedx);
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#endif
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real_main(bist, cpu_init_detectedx);
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#endif
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}
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#if CONFIG_USE_FAILOVER_IMAGE==0
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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static const uint16_t spd_addr [] = {
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(0xa<<3)|0, (0xa<<3)|2, 0, 0,
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@ -248,7 +135,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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bsp_apicid = init_cpus(cpu_init_detectedx);
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}
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// post_code(0x32);
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post_code(0x32);
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lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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@ -310,4 +197,3 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_cache_as_ram();
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}
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#endif
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@ -0,0 +1,108 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#define post_code(x) outb(x, 0x80)
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#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
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#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
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#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
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#define SUPERIO_GPIO_IO_BASE 0x400
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static void sio_setup(void)
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{
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unsigned value;
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uint32_t dword;
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uint8_t byte;
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
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byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1<<29)|(1<<0);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
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dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
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dword |= (1<<16);
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pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
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lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
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value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
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value &= 0xbf;
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lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
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}
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void mainboard_bsp_init()
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{
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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sio_setup();
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/* Setup the ck804 */
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ck804_enable_rom();
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}
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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unsigned last_boot_normal_x = last_boot_normal();
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/* Is this a cpu only reset? or Is this a secondary cpu? */
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if ((cpu_init_detectedx) || (!boot_cpu())) {
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if (last_boot_normal_x) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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}
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mainboard_bsp_init();
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/* Is this a deliberate reset by the bios */
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post_code(0x22);
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if (bios_reset_detected() && last_boot_normal_x) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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normal_image:
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post_code(0x23);
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__asm__ volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
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);
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fallback_image:
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post_code(0x25);
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__asm__ volatile ("jmp __fallback_image"
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: /* outputs */
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: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
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);
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}
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