nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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c583920a74
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7843bd560e
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@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE
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hex
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default 0x4000 # 16 kB
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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config DCACHE_RAM_BASE
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hex
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default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
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@ -13,7 +13,14 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
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cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
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else
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bootblock-y += ../car/p4-netburst/cache_as_ram.S
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bootblock-y += ../car/bootblock.c
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bootblock-y += ../../x86/early_reset.S
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endif
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postcar-y += ../car/p4-netburst/exit_car.S
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romstage-y += ../car/romstage.c
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@ -1,4 +1,7 @@
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ramstage-y += cstates.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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@ -27,7 +28,7 @@
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#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
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#define SUPERIO_DEV PNP_DEV(0x2e, 0)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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/* Set GPIOs on superio, enable UART */
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if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {
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@ -13,5 +13,8 @@
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CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C))
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-y += cstates.c
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romstage-y += $(CONFIG_GPIO_C)
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@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <superio/winbond/w83667hg-a/w83667hg-a.h>
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@ -21,7 +22,7 @@
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#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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/* TODO? */
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RCBA32(RCBA_CG) = 0xbf7f001f;
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@ -11,6 +11,9 @@
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# GNU General Public License for more details.
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#
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bootblock-y += early_init.c
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romstage-y += gpio.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -12,6 +12,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#include <northbridge/intel/x4x/x4x.h>
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@ -24,7 +25,7 @@
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -1,4 +1,7 @@
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ramstage-y += cstates.c
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romstage-y += variants/$(VARIANT_DIR)/gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <cf9_reset.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -1,6 +1,9 @@
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/
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@ -16,6 +16,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/ite/common/ite.h>
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@ -24,7 +25,7 @@
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#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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/* Set up GPIOs on Super I/O. */
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ite_reg_write(GPIO_DEV, 0x25, 0x01);
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@ -1,4 +1,7 @@
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -14,6 +14,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <northbridge/intel/x4x/x4x.h>
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* We should use standard gpio.h eventually
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*/
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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pci_devfn_t dev;
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@ -1,4 +1,7 @@
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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/* Set GPIOs on superio, enable UART */
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pnp_enter_ext_func_mode(SERIAL_DEV);
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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RCBA32(0x3410) = 0x00060464;
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RCBA32(RCBA_BUC) &= ~BUC_LAND;
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@ -1,4 +1,7 @@
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ramstage-y += cstates.c
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romstage-y += gpio.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -15,12 +15,13 @@
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <superio/smsc/smscsuperio/smscsuperio.h>
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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void mb_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select INTEL_GMA_ACPI
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select CACHE_MRC_SETTINGS
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select PARALLEL_MP
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select C_ENVIRONMENT_BOOTBLOCK
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config CBFS_SIZE
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hex
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default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/x4x/bootblock.c"
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config VGA_BIOS_ID
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string
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default "8086,2e32"
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
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bootblock-y += bootblock.c
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romstage-y += early_init.c
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romstage-y += raminit.c
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romstage-y += raminit_ddr23.c
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*/
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#include <device/pci_ops.h>
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#include <cpu/intel/car/bootblock.h>
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#include "x4x.h"
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#include "iomap.h"
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/* Just re-define these instead of including x4x.h. It blows up romcc. */
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#define D0F0_PCIEXBAR_LO 0x60
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#define D0F0_PCIEXBAR_HI 0x64
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static void bootblock_northbridge_init(void)
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void bootblock_early_northbridge_init(void)
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{
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uint32_t reg32;
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u8 boot_path = 0;
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u8 s3_resume;
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
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i82801jx_lpc_setup();
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#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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i82801gx_lpc_setup();
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#endif
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mb_lpc_setup();
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console_init();
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enable_smbus();
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
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void x4x_early_init(void);
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void x4x_late_init(int s3resume);
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void mb_lpc_setup(void);
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void mb_get_spd_map(u8 spd_map[4]);
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void mb_pre_raminit_setup(int s3_resume);
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u32 decode_igd_memory_size(u32 gms);
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config HPET_MIN_TICKS
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hex
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default 0x80
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/i82801jx/bootblock.c"
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endif
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y)
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bootblock-y += bootblock.c
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bootblock-y += early_init.c
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ramstage-y += i82801jx.c
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ramstage-y += pci.c
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ramstage-y += lpc.c
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*/
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#include <device/pci_ops.h>
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#include <cpu/intel/car/bootblock.h>
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#include "i82801jx.h"
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static void enable_spi_prefetch(void)
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pci_write_config8(dev, 0xdc, reg8);
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}
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static void bootblock_southbridge_init(void)
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void bootblock_early_southbridge_init(void)
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{
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enable_spi_prefetch();
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/* Enable RCBA */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
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(uintptr_t)DEFAULT_RCBA | 1);
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i82801jx_setup_bars();
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/* Enable upper 128bytes of CMOS. */
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RCBA32(0x3400) = (1 << 2);
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i82801jx_lpc_setup();
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}
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pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
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}
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static void i82801jx_setup_bars(void)
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void i82801jx_setup_bars(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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const u8 *buf);
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#endif
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void i82801jx_lpc_setup(void);
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void i82801jx_setup_bars(void);
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void i82801jx_early_init(void);
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#endif
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