nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK

There is some overlap between things done in bootblock
and romstage like setting BARs.

Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-11 21:56:37 +01:00 committed by Patrick Georgi
parent c583920a74
commit 7843bd560e
30 changed files with 72 additions and 39 deletions

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@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE
hex
default 0x4000 # 16 kB
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
config DCACHE_RAM_BASE
hex
default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE

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@ -13,7 +13,14 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
else
bootblock-y += ../car/p4-netburst/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S
endif
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

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@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
@ -27,7 +28,7 @@
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
/* Set GPIOs on superio, enable UART */
if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {

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@ -13,5 +13,8 @@
CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C))
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-y += cstates.c
romstage-y += $(CONFIG_GPIO_C)

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <northbridge/intel/x4x/x4x.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
@ -21,7 +22,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
/* TODO? */
RCBA32(RCBA_CG) = 0xbf7f001f;

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@ -11,6 +11,9 @@
# GNU General Public License for more details.
#
bootblock-y += early_init.c
romstage-y += gpio.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -12,6 +12,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <console/console.h>
#include <northbridge/intel/x4x/x4x.h>
@ -24,7 +25,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h>
#include <console/console.h>
@ -27,7 +28,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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@ -1,6 +1,9 @@
ramstage-y += cstates.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/

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@ -16,6 +16,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/ite/common/ite.h>
@ -24,7 +25,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
/* Set up GPIOs on Super I/O. */
ite_reg_write(GPIO_DEV, 0x25, 0x01);

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@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/x4x/x4x.h>
@ -29,7 +30,7 @@
* We should use standard gpio.h eventually
*/
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
pci_devfn_t dev;

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@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
@ -23,7 +24,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
/* Set GPIOs on superio, enable UART */
pnp_enter_ext_func_mode(SERIAL_DEV);

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@ -14,4 +14,7 @@
ramstage-y += cstates.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <northbridge/intel/x4x/x4x.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
@ -21,7 +22,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
RCBA32(0x3410) = 0x00060464;
RCBA32(RCBA_BUC) &= ~BUC_LAND;

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@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += gpio.c
bootblock-y += early_init.c
romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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@ -15,12 +15,13 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <northbridge/intel/x4x/x4x.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
void mb_lpc_setup(void)
void bootblock_mainboard_early_init(void)
{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

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@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS
select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK
config CBFS_SIZE
hex
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/x4x/bootblock.c"
config VGA_BIOS_ID
string
default "8086,2e32"

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@ -16,6 +16,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y)
bootblock-y += bootblock.c
romstage-y += early_init.c
romstage-y += raminit.c
romstage-y += raminit_ddr23.c

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@ -15,13 +15,11 @@
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "x4x.h"
#include "iomap.h"
/* Just re-define these instead of including x4x.h. It blows up romcc. */
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
static void bootblock_northbridge_init(void)
void bootblock_early_northbridge_init(void)
{
uint32_t reg32;

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@ -34,16 +34,6 @@ void mainboard_romstage_entry(void)
u8 boot_path = 0;
u8 s3_resume;
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)
i82801jx_lpc_setup();
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
i82801gx_lpc_setup();
#endif
mb_lpc_setup();
console_init();
enable_smbus();
#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX)

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@ -373,7 +373,6 @@ enum ddr2_signals {
void x4x_early_init(void);
void x4x_late_init(int s3resume);
void mb_lpc_setup(void);
void mb_get_spd_map(u8 spd_map[4]);
void mb_pre_raminit_setup(int s3_resume);
u32 decode_igd_memory_size(u32 gms);

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@ -51,9 +51,4 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
config HPET_MIN_TICKS
hex
default 0x80
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801jx/bootblock.c"
endif

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@ -16,6 +16,9 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y)
bootblock-y += bootblock.c
bootblock-y += early_init.c
ramstage-y += i82801jx.c
ramstage-y += pci.c
ramstage-y += lpc.c

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@ -14,6 +14,7 @@
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "i82801jx.h"
static void enable_spi_prefetch(void)
@ -29,14 +30,14 @@ static void enable_spi_prefetch(void)
pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
(uintptr_t)DEFAULT_RCBA | 1);
i82801jx_setup_bars();
/* Enable upper 128bytes of CMOS. */
RCBA32(0x3400) = (1 << 2);
i82801jx_lpc_setup();
}

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@ -56,7 +56,7 @@ void i82801jx_lpc_setup(void)
pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
}
static void i82801jx_setup_bars(void)
void i82801jx_setup_bars(void)
{
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);

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@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
#endif
void i82801jx_lpc_setup(void);
void i82801jx_setup_bars(void);
void i82801jx_early_init(void);
#endif