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Remove XIP_ROM_BASE 

The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2011-10-31 17:07:52 +01:00 committed by Stefan Reinauer
parent 36c04e8a5c
commit 784544b934
17 changed files with 12 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/amd/agesa/family10/Kconfig
View File

@ -40,10 +40,6 @@ config CDB
hex
default 0x18
config XIP_ROM_BASE
hex
default 0xfff80000
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/agesa/family12/Kconfig
View File

@ -57,11 +57,6 @@ config CDB
default 0x18
depends on CPU_AMD_AGESA_FAMILY12
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_AGESA_FAMILY12
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/agesa/family14/Kconfig
View File

@ -57,11 +57,6 @@ config CDB
default 0x18
depends on CPU_AMD_AGESA_FAMILY14
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_AGESA_FAMILY14
config XIP_ROM_SIZE
hex
default 0x80000

4
src/cpu/amd/car/cache_as_ram.inc
View File

@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out:
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_XIP_ROM_SIZE
/* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out:
wbcache_post_fam10_setup:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx

5
src/cpu/amd/socket_AM2r2/Kconfig
View File

@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_AM2R2
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_AM2R2
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/socket_AM3/Kconfig
View File

@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_AM3
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_AM3
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/socket_ASB2/Kconfig
View File

@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_ASB2
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_ASB2
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/socket_C32/Kconfig
View File

@ -30,11 +30,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_C32
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_C32
config XIP_ROM_SIZE
hex
default 0x80000

5
src/cpu/amd/socket_F_1207/Kconfig
View File

@ -29,11 +29,6 @@ config CDB
default 0x18
depends on CPU_AMD_SOCKET_F_1207
config XIP_ROM_BASE
hex
default 0xfff80000
depends on CPU_AMD_SOCKET_F_1207
config XIP_ROM_SIZE
hex
default 0x80000

4
src/cpu/intel/car/cache_as_ram.inc
View File

@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_XIP_ROM_SIZE
/*
* Enable write base caching so we can do execute in place (XIP)
@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax

4
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -98,7 +98,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@ -115,7 +115,7 @@ clear_mtrrs:
xorl %edx, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax

4
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -98,7 +98,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@ -115,7 +115,7 @@ clear_mtrrs:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax

4
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -105,7 +105,7 @@ clear_mtrrs:
orl $(1 << 30), %eax
movl %eax, %cr0
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
@ -122,7 +122,7 @@ clear_mtrrs:
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */
movl %cr0, %eax

2
src/cpu/via/car/cache_as_ram.inc
View File

@ -240,7 +240,7 @@ testok:
movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
/* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
/* Cache XIP_ROM area to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
/*

4
src/cpu/x86/Kconfig
View File

@ -27,10 +27,6 @@ config TSC_CALIBRATE_WITH_IO
bool
default n
config XIP_ROM_BASE
hex
default 0xffff0000
config XIP_ROM_SIZE
hex
default 0x10000

12
src/include/cpu/x86/mtrr.h
View File

@ -45,23 +45,13 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
void x86_setup_fixed_mtrrs(void);
#endif
/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
#endif
#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
#endif
#if !defined(CONFIG_RAMTOP)
# error "CONFIG_RAMTOP not defined"
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"

5
src/mainboard/supermicro/h8dmr_fam10/README
View File

@ -21,8 +21,3 @@ See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/
Ward, 2009-09-22
mansoor@iwavesystems.com said, about the last issue:
Try enabling CONFIG_XIP_ROM_BASE. It solved the same problem for me in my board.
So, that's a todo.