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cpu/intel/p4-netburst: skip caching rom on model_fxx 

An unidentified combination of speculative reads and branch
predictions inside WRPROT-cacheable memory can cause invalidation of
cachelines and loss of stack on models based on NetBurst
microarchitecture.

Therefore disable WRPROT region entirely for all family F models.

As an extreme example, just changing the location of a constant string
passed to printk() has been witnessed to make a the boot fail early on
in romstage.

Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2018-06-16 20:01:47 +02:00 committed by Kyösti Mälkki
parent ce9f422b51
commit 7875dbd981
1 changed files with 14 additions and 0 deletions
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14
src/cpu/intel/car/p4-netburst/cache_as_ram.S
View File

@ -315,6 +315,18 @@ no_msr_11e:
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
/*
* An unidentified combination of speculative reads and branch
* predictions inside WRPROT-cacheable memory can cause invalidation
* of cachelines and loss of stack on models based on NetBurst
* microarchitecture. Therefore disable WRPROT region entirely for
* all family F models.
*/
movl $1, %eax
cpuid
cmp $0xf, %ah
je skip_cache_rom
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
@ -332,6 +344,8 @@ no_msr_11e:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
skip_cache_rom:
post_code(0x2e)
/* Enable cache. */
movl %cr0, %eax