fsp1_1: provide binding to UEFI version

FSP has some unique attributes which makes integration
cumbersome:

1. FSP header files do not include the types they need. Like
   EDKII development it's expected types are provided by the
   build system. Therefore, one needs to include the proper
   files to avoid compilation issues.
2. An implementation of FSP for a chipset may use different
   versions of the UEFI PI spec implementation. EDKII is a
   proxy for all of UEFI specifications. In order to provide
   flexibility one needs to binding a set of types and
   structures from an UEFI PI implementation.
3. Each chipset FSP 1.1 implementation has a FspUpdVpd.h
   file which defines it's own types. Commonality between
   FSP chipset implementations are only named typedef
   structs. The fields within are not consistent. And
   because of FSP's insistence on typedefs it makes it
   near impossible to forward declare structs.

The above 3 means one needs to include the correct UEFI
type bindings when working with FSP. The current
implementation had the SoC picking include paths in the
edk2 directory and using a bare <uefi_types.h> include.
Also, with the prior fsp_util.h implementation the SoC's
FSP FspUpdVpd.h header file was required since for providing
all the types at once (Generic FSP 1.1 and SoC types).

The binding has been changed in the following manner:
1. CONFIG_UEFI_2_4_BINDING option added which FSP 1.1
   selects. No other bindings are currently available,
   but this provides the policy.
2. Based on CONFIG_UEFI_2_4_BINDING the proper include
   paths are added to the CPPFLAGS_common.
3. SoC Makefile.inc does not bind UEFI types nor does
   it adjust CPPFLAGS_common in any way.
4. Provide a include/fsp directory under fsp1_1 and
   expose src/drivers/intel/fsp1_1/include in the
   include path. This split can allow a version 2,
   for example, FSP to provide its own include files.
   Yes, that means there needs to be consistency in
   APIs, however that's not this patch.
5. Provide a way for code to differentiate the FSP spec
   types (fsp/api.h) from the chipset FSP types
   (fsp/soc_binding.h). This allows for code re-use that
   doesn't need the chipset types to be defined such as
   the FSP relocation code.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted on glados.

Signed-off-by: Aaron Durbin <adubin@chromium.org>

Change-Id: I894165942cfe36936e186af5221efa810be8bb29
Reviewed-on: http://review.coreboot.org/11606
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)

src/drivers/intel/fsp1_1/Kconfig

@@ -19,6 +19,7 @@
 
 config PLATFORM_USES_FSP1_1
 	bool
+	select UEFI_2_4_BINDING
 	help
 	  Does the code require the Intel Firmware Support Package?
 

src/drivers/intel/fsp1_1/Makefile.inc

@@ -26,7 +26,9 @@ ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
 
-CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1
+CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
+# Where FspUpdVpd.h can be picked up from.
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
 
 cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
 

src/drivers/intel/fsp1_1/fsp_gop.c

@@ -19,7 +19,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <lib.h>
 
 /* Reading VBT table from flash */

src/drivers/intel/fsp1_1/fsp_relocate.c

@@ -19,11 +19,10 @@
 
 #include <console/console.h>
 #include <cbmem.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <string.h>
-#include <uefi_types.h>
 
 #define FSP_DBG_LVL BIOS_NEVER
 

src/drivers/intel/fsp1_1/fsp_util.c

@@ -21,7 +21,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <timestamp.h>
 
 /* Locate the FSP binary in the coreboot filesystem */

src/drivers/intel/fsp1_1/hob.c

@@ -23,7 +23,7 @@
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "fsp_util.h"
+#include <fsp/util.h>
 #include <ip_checksum.h>
 #include <lib.h> // hexdump
 #include <string.h>

src/drivers/intel/fsp1_1/include/fsp/api.h

@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_API_H_
+#define _FSP1_1_API_H_
+
+#define FSP_SIG		0x48505346	/* 'FSPH' */
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h>
+#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif

src/drivers/intel/fsp1_1/include/fsp/gop.h

@@ -17,8 +17,8 @@
  * Foundation, Inc.
  */
 
-#ifndef _FSP_GOP_H_
-#define _FSP_GOP_H_
+#ifndef _FSP1_1_GOP_H_
+#define _FSP1_1_GOP_H_
 
 /* GOP support */
 #if IS_ENABLED(CONFIG_GOP_SUPPORT)

src/drivers/intel/fsp1_1/include/fsp/soc_binding.h

@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_SOC_BINDING_H_
+#define _FSP1_1_SOC_BINDING_H_
+
+/* All the FSP headers need to have UEFI types provided before inclusion. */
+#include <fsp/uefi_binding.h>
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * This file is found by way of the Kconfig FSP_INCLUDE_PATH option. It is
+ * a per implementation specific header. i.e. different FSP implementations
+ * for different chipsets.
+ */
+#include <FspUpdVpd.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif

src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h

@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _FSP1_1_UEFI_BINDING_H_
+#define _FSP1_1_UEFI_BINDING_H_
+
+/*
+ * Intel's code does not have a handle on changing global packing state.
+ * Therefore, one needs to protect against packing policies that are set
+ * globally for a compliation unit just by including a header file.
+ */
+#pragma pack(push)
+
+/*
+ * Pull in the UEFI types from 2.4. Smarter decisions can be made on what
+ * version to bind to, but for now 2.4 is standard for FSP 1.1.
+ */
+#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h>
+
+/* Restore original packing policy. */
+#pragma pack(pop)
+
+#endif

src/drivers/intel/fsp1_1/include/fsp/util.h

@@ -18,29 +18,16 @@
  * Foundation, Inc.
  */
 
-#ifndef FSP_UTIL_H
-#define FSP_UTIL_H
+#ifndef FSP1_1_UTIL_H
+#define FSP1_1_UTIL_H
 
-#include <types.h>
-#include <arch/cpu.h>
-#include <fsp_gop.h>
+#include <fsp/api.h>
+/* Current users expect to get the SoC's FSP definitions by including util.h. */
+#include <fsp/soc_binding.h>
+#include <fsp/gop.h>
 #include <program_loading.h>
 #include <region.h>
 
-/*
- * The following are functions with prototypes defined in the EDK2 headers. The
- * EDK2 headers are included with chipset_fsp_util.h.  Define the following
- * names to reduce the use of CamelCase in the other source files.
- */
-#define GetHobList	get_hob_list
-#define GetNextHob	get_next_hob
-#define GetFirstHob	get_first_hob
-#define GetNextGuidHob	get_next_guid_hob
-#define GetFirstGuidHob	get_first_guid_hob
-
-/* Include the EDK2 headers */
-#include <soc/chipset_fsp_util.h>
-
 /* find_fsp() should only be called from assembly code. */
 FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address);
 /* Set FSP's runtime information. */
@@ -88,8 +75,6 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
 #define FSP_IMAGE_ATTRIBUTE_LOC			32
 #define  GRAPHICS_SUPPORT_BIT			(1 << 0)
 
-#define FSP_SIG					0x48505346	/* 'FSPH' */
-
 #define ERROR_NO_FV_SIG				1
 #define ERROR_NO_FFS_GUID			2
 #define ERROR_NO_INFO_HEADER			3
@@ -101,4 +86,11 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
 extern void *FspHobListPtr;
 #endif
 
-#endif	/* FSP_UTIL_H */
+/* TODO: Remove the EFI types and decorations from coreboot implementations. */
+VOID * EFIAPI get_hob_list(VOID);
+VOID * EFIAPI get_next_hob(UINT16 type, CONST VOID *hob_start);
+VOID * EFIAPI get_first_hob(UINT16 type);
+VOID * EFIAPI get_next_guid_hob(CONST EFI_GUID * guid, CONST VOID *hob_start);
+VOID * EFIAPI get_first_guid_hob(CONST EFI_GUID * guid);
+
+#endif	/* FSP1_1_UTIL_H */

src/soc/intel/braswell/Makefile.inc

@@ -51,19 +51,11 @@ smm-y += smihandler.c
 smm-y += spi.c
 smm-y += tsc_freq.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/
 CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
 
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS

src/soc/intel/braswell/acpi.c

@@ -35,7 +35,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <ec/google/chromeec/ec.h>
-#include <fsp_gop.h>
+#include <fsp/gop.h>
 #include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>

src/soc/intel/braswell/chip.c

@@ -22,7 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 

src/soc/intel/braswell/chip.h

@@ -27,7 +27,7 @@
 #define _SOC_CHIP_H_
 
 #include <stdint.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 
 #define SVID_CONFIG1		1

src/soc/intel/braswell/include/soc/chipset_fsp_util.h

@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef CHIPSET_FSP_UTIL_H
-#define CHIPSET_FSP_UTIL_H
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* CHIPSET_FSP_UTIL_H */

src/soc/intel/braswell/include/soc/romstage.h

@@ -23,7 +23,7 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
 #include <soc/intel/common/romstage.h>

src/soc/intel/braswell/northcluster.c

@@ -25,7 +25,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>

src/soc/intel/braswell/ramstage.c

@@ -29,7 +29,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <romstage_handoff.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>

src/soc/intel/braswell/romstage/romstage.c

@@ -40,7 +40,7 @@
 #include <timestamp.h>
 #include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>

src/soc/intel/common/fsp_ramstage.c

@@ -22,7 +22,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/memmap.h>
 #include <soc/intel/common/ramstage.h>

src/soc/intel/common/raminit.c

@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h> /* hexdump */
 #include <reset.h>
 #include <soc/intel/common/memmap.h>

src/soc/intel/common/ramstage.h

@@ -21,7 +21,7 @@
 #ifndef _INTEL_COMMON_RAMSTAGE_H_
 #define _INTEL_COMMON_RAMSTAGE_H_
 
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <stdint.h>
 

src/soc/intel/common/romstage.h

@@ -24,7 +24,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <memory_info.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/intel/common/util.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>		/* chip_power_state */

src/soc/intel/common/vbt.c

@@ -20,7 +20,7 @@
 
 #include <cbfs.h>
 #include <console/console.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <lib.h>
 #include <soc/intel/common/ramstage.h>
 #include <string.h>

src/soc/intel/skylake/Makefile.inc

@@ -61,19 +61,12 @@ smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_UART_DEBUG) += uart_debug.c
 
-CPPFLAGS_common += -I$(src)/arch/x86/include/
 CPPFLAGS_common += -I$(src)/soc/intel/skylake
 CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
 
+# Currently used for microcode path.
 CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
 
-CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
-CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
-CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
-
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS

src/soc/intel/skylake/chip.c

@@ -23,7 +23,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp_util.h>
+#include <fsp/util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <string.h>

src/soc/intel/skylake/include/soc/chipset_fsp_util.h

@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#ifndef _CHIPSET_FSP_UTIL_H_
-#define _CHIPSET_FSP_UTIL_H_
-
-/*
- * Include the FSP binary interface files
- *
- * These files include the necessary UEFI constants and data structures
- * that are used to interface to the FSP binary.
- */
-
-#include <uefi_types.h>				/* UEFI data types */
-#include <IntelFspPkg/Include/FspApi.h>		/* FSP API definitions */
-#include <IntelFspPkg/Include/FspInfoHeader.h>	/* FSP binary layout */
-#include <MdePkg/Include/Pi/PiBootMode.h>	/* UEFI boot mode definitions */
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>	/* UEFI file definitions */
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>	/* UEFI file system defs */
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>	/* UEFI memory types */
-#include <MdePkg/Include/Pi/PiHob.h>		/* Hand off block definitions */
-#include <MdePkg/Include/Library/HobLib.h>	/* HOB routine declarations */
-#include <FspUpdVpd.h>		/* Vital/updatable product data definitions */
-
-#endif	/* _CHIPSET_FSP_UTIL_H_ */

src/soc/intel/skylake/ramstage.c

@@ -18,9 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <bootstate.h>
-#include <console/console.h>
-#include <fsp_util.h>
 #include <soc/ramstage.h>
 #include <soc/intel/common/ramstage.h>
 

src/vendorcode/intel/Kconfig

@@ -22,3 +22,6 @@ config FSP_VENDORCODE_HEADER_PATH
 	default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
 	default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL
 	default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX
+
+config UEFI_2_4_BINDING
+	def_bool n

src/vendorcode/intel/Makefile.inc

@@ -25,3 +25,13 @@ ramstage-y += $(FSP_C_INPUTS)
 
 CFLAGS_x86_32 += -Isrc/vendorcode/intel/$(FSP_PATH)/include
 endif
+
+ifeq ($(CONFIG_UEFI_2_4_BINDING),y)
+# ProccessorBind.h provided in Ia32 directory. Types are derived from ia32.
+# It's possible to provide our own ProcessorBind.h using posix types. However,
+# ProcessorBind.h isn't just about types. There's compiler definitions as well
+# as ABI enforcement. Luckily long is not used in Ia32/ProcessorBind.h for
+# a fixed width type.
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+endif

src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h

@@ -37,15 +37,15 @@ are permitted provided that the following conditions are met:
 #define __APPLE__ 0
 #include <stdlib.h>
 #include <Uefi/UefiBaseType.h>
-#include <MdePkg/Include/Pi/PiBootMode.h>
-#include <MdePkg/Include/Pi/PiFirmwareFile.h>
-#include <MdePkg/Include/Pi/PiFirmwareVolume.h>
-#include <MdePkg/Include/Uefi/UefiMultiPhase.h>
-#include <MdePkg/Include/Pi/PiHob.h>
-#include <MdePkg/Include/Protocol/GraphicsOutput.h>
-#include <MdePkg/Include/Library/HobLib.h>
-#include <MdePkg/Include/Guid/FirmwareFileSystem2.h>
-#include <MdePkg/Include/IndustryStandard/PeImage.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiFirmwareVolume.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiHob.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Library/HobLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <IndustryStandard/PeImage.h>
 
 ///
 /// For GNU assembly code, .global or .globl can declare global symbols.