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FUI: reorganize include files 

We've got enough of a handle on this to realize some things:
drm_dp_helper.h is by design device and architecture independent
i915.h is common to most intel graphics chipsets going back several years
i915_reg.h is as well

Move these files to src/include/device, and adjust the .c files accordingly.

Change-Id: I07512b3695fea0b22949074b467986420783d62a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich 2013-04-24 09:50:56 -07:00 committed by Stefan Reinauer
parent b2893a0169
commit 78c3e33550
8 changed files with 39 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
src/northbridge/intel/haswell/drm_dp_helper.h → src/include/device/drm_dp_helper.h
View File

38
src/mainboard/intel/wtm2/i915io.h → src/include/device/i915.h
View File

@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <northbridge/intel/haswell/i915_reg.h>
#include <northbridge/intel/haswell/drm_dp_helper.h>
#include <device/i915_reg.h>
#include <device/drm_dp_helper.h>
/* things that are, strangely, not defined anywhere? */
#define PCH_PP_UNLOCK 0xabcd0000
@ -29,28 +29,6 @@
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
/* mainboard-specific defines */
/* how many bytes do we need for the framebuffer?
* Well, this gets messy. To get an exact answer, we have
* to ask the panel, but we'd rather zero the memory
* and set up the gtt while the panel powers up. So,
* we take a reasonable guess, secure in the knowledge that the
* MRC has to overestimate the number of bytes used.
* 8 MiB is a very safe guess. There may be a better way later, but
* fact is, the initial framebuffer is only very temporary. And taking
* a little long is ok; this is done much faster than the AUX
* channel is ready for IO.
*/
#define FRAME_BUFFER_BYTES (8*MiB)
/* how many 4096-byte pages do we need for the framebuffer?
* There are hard ways to get this, and easy ways:
* there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
* on this chip.
*/
#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
/* debug enums. These are for printks that, due to their place in the
* middle of graphics device IO, might change timing. Use with care
* or not at all.
@ -60,11 +38,10 @@ enum {
vspin = 4, /* print # of times we spun on a register value */
};
/* i915.c */
unsigned long io_i915_READ32(unsigned long addr);
void io_i915_WRITE32(unsigned long val, unsigned long addr);
int vbe_mode_info_valid(void);
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
/* The mainboard must provide these functions. */
unsigned long io_i915_read32(unsigned long addr);
void io_i915_write32(unsigned long val, unsigned long addr);
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose);
/* intel_dp.c */
u32 pack_aux(u32 *src, int src_bytes);
@ -72,5 +49,4 @@ void unpack_aux(u32 src, u8 *dst, int dst_bytes);
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
u8 *recv, int recv_size);
/* i915io.c */
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose);

0
src/northbridge/intel/haswell/i915_reg.h → src/include/device/i915_reg.h
View File

1
src/include/edid.h
View File

@ -66,5 +66,6 @@ struct edid {
/* Defined in src/lib/edid.c */
int decode_edid(unsigned char *edid, int size, struct edid *out);
void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr);
#endif /* EDID_H */

1
src/lib/edid.c
View File

@ -1395,7 +1395,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
* Take an edid, and create a framebuffer. Set vbe_valid to 1.
*/
void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr);
void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
{
edid_fb.physical_address = fb_addr;

2
src/mainboard/intel/wtm2/graphics.c
View File

@ -20,7 +20,7 @@
* will be all machine generated. Avoid editing.
*/
#include <console/console.h>
#include "i915io.h"
#include <device/i915.h>
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
{

110
src/mainboard/intel/wtm2/i915.c
View File

@ -42,7 +42,26 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <edid.h>
#include "i915io.h"
#include <device/i915.h>
/* how many bytes do we need for the framebuffer?
* Well, this gets messy. To get an exact answer, we have
* to ask the panel, but we'd rather zero the memory
* and set up the gtt while the panel powers up. So,
* we take a reasonable guess, secure in the knowledge that the
* MRC has to overestimate the number of bytes used.
* 8 MiB is a very safe guess. There may be a better way later, but
* fact is, the initial framebuffer is only very temporary. And taking
* a little long is ok; this is done much faster than the AUX
* channel is ready for IO.
*/
#define FRAME_BUFFER_BYTES (8*MiB)
/* how many 4096-byte pages do we need for the framebuffer?
* There are hard ways to get this, and easy ways:
* there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
* on this chip (and in fact every Intel graphics chip we've seen).
*/
#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
static int verbose = 0;
@ -139,95 +158,6 @@ static unsigned long globalmicroseconds(void)
static int i915_init_done = 0;
/* fill the palette. This runs when the P opcode is hit. */
static void palette(void)
{
int i;
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
}
}
static unsigned long times[4096];
static int run(int index)
{
int i, prev = 0;
struct iodef *id, *lastidread = 0;
unsigned long u, t;
if (index >= niodefs)
return index;
/* state machine! */
for(i = index, id = &iodefs[i]; id->op; i++, id++){
switch(id->op){
case M:
if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
globalmicroseconds(), id->msg);
break;
case P:
palette();
break;
case R:
u = READ32(id->addr);
if (verbose & vio)
printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
/* we're looking for something. */
if (lastidread->addr == id->addr){
/* they're going to be polling.
* just do it 1000 times
*/
for(t = 0; t < 1000 && id->data != u; t++){
u = READ32(id->addr);
}
if (verbose & vspin) printk(BIOS_SPEW,
"%s: # loops %ld got %08lx want %08lx\n",
regname(id->addr),
t, u, id->data);
}
lastidread = id;
break;
case W:
WRITE32(id->data, id->addr);
if (id->addr == PCH_PP_CONTROL){
if (verbose & vio)
printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
switch(id->data & 0xf){
case 8: break;
case 7: break;
default: udelay(100000);
if (verbose & vio)
printk(BIOS_SPEW, "U %d\n", 100000);
}
}
break;
case V:
if (id->count < 8){
prev = verbose;
verbose = id->count;
} else {
verbose = prev;
}
printk(BIOS_SPEW, "Change verbosity to %d\n", verbose);
break;
case I:
printk(BIOS_SPEW, "run: return %d\n", i+1);
return i+1;
break;
default:
printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
return -1;
}
if (id->udelay)
udelay(id->udelay);
if (i < ARRAY_SIZE(times))
times[i] = globalmicroseconds();
}
printk(BIOS_SPEW, "run: return %d\n", i);
return i+1;
}
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx);

20
src/mainboard/intel/wtm2/intel_dp.c
View File

@ -30,7 +30,7 @@
#include <console/console.h>
#include <stdint.h>
#include <delay.h>
#include "i915io.h"
#include <device/i915.h>
u32
pack_aux(u32 *src32, int src_bytes)
@ -79,7 +79,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
/* Try to wait for any previous AUX channel activity */
for (try = 0; try < 3; try++) {
status = io_i915_READ32(ch_ctl);
status = io_i915_read32(ch_ctl);
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
break;
udelay(1000);
@ -87,8 +87,9 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
if (try == 3) {
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
io_i915_READ32(ch_ctl));
status = io_i915_read32(ch_ctl);
printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08x\n",
status);
return -1;
}
@ -96,10 +97,10 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
for (try = 0; try < 5; try++) {
/* Load the send data into the aux channel data registers */
for (i = 0; i < send_bytes; i += 4)
io_i915_WRITE32(send[i], ch_data + i);
io_i915_write32(send[i], ch_data + i);
/* Send the command and wait for it to complete */
io_i915_WRITE32(
io_i915_write32(
DP_AUX_CH_CTL_SEND_BUSY |
DP_AUX_CH_CTL_TIME_OUT_400us |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
@ -109,14 +110,14 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
for (;;) {
status = io_i915_READ32(ch_ctl);
status = io_i915_read32(ch_ctl);
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
break;
udelay(100);
}
/* Clear done status and any errors */
io_i915_WRITE32(
io_i915_write32(
status |
DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_TIME_OUT_ERROR |
@ -159,9 +160,8 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
recv_bytes = recv_size;
for (i = 0; i < recv_bytes; i += 4)
unpack_aux(io_i915_READ32(ch_data + i),
unpack_aux(io_i915_read32(ch_data + i),
recv + i, recv_bytes - i);
return recv_bytes;
}