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soc/intel/meteorlake: Enable tbtPcie2/3 

Adding support enables/disables tbtPcie2/3 by usb4_params.

BUG=b:244687646
TEST= TRP2/3 are enabled as expected.
before patch
[INFO ]  PCI: Static device PCI: 00:07.2 not found, disabling it.
[INFO ]  PCI: Static device PCI: 00:07.3 not found, disabling it.
after patch
[DEBUG]  PCI: 00:07.2 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.2 [8086/7ec6] enabled
[DEBUG]  PCI: 00:07.3 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.3 [8086/7ec7] enabled

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Ivy Jian 2022-09-12 13:19:11 +08:00 committed by Subrata Banik
parent e5c547c2d7
commit 78c4d0f6a6
1 changed files with 2 additions and 0 deletions
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2
src/soc/intel/meteorlake/romstage/fsp_params.c
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@ -230,6 +230,8 @@ static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssItbtPcie0En = !(config->tbt_pcie_port_disable[0]); m_cfg->TcssItbtPcie0En = !(config->tbt_pcie_port_disable[0]);
m_cfg->TcssItbtPcie1En = !(config->tbt_pcie_port_disable[1]); m_cfg->TcssItbtPcie1En = !(config->tbt_pcie_port_disable[1]);
m_cfg->TcssItbtPcie2En = !(config->tbt_pcie_port_disable[2]);
m_cfg->TcssItbtPcie3En = !(config->tbt_pcie_port_disable[3]);
} }
static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,