mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6
The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -51,7 +51,6 @@ chip northbridge/intel/pineview # Northbridge
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end
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end
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device pci 1c.2 off end # PCIe 3
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1c.3 off end # PCIe 4
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# (PCIe 5 and 6 not on nm10?)
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device pci 1d.0 on end # USB
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.2 on end # USB
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@ -49,7 +49,6 @@ chip northbridge/intel/pineview # Northbridge
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device pci 1c.1 on end # PCIe 2
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device pci 1c.1 on end # PCIe 2
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device pci 1c.2 on end # PCIe 3
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device pci 1c.2 on end # PCIe 3
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device pci 1c.3 on end # PCIe 4
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device pci 1c.3 on end # PCIe 4
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# (PCIe 5 and 6 not on nm10?)
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device pci 1d.0 on end # USB
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.2 on end # USB
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