soc/intel/apollolake: Implement _PS0/_PS3 methods for PCIe root ports
Creates a common asl include file for PCIe power state methods. This allows ports to be enabled independently. BUG=None BRANCH=None TEST=None Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/25532 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Include in each PCIe Root Port device */
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/* lowest D-state supported by
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* PCIe root port during S0 state
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*/
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Name (_S0W, 4)
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Name (PDST, 0) /* present Detect status */
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/* Dynamic Opregion needed to access registers
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* when the controller is in D3 cold
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*/
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OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
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Field (PX01, AnyAcc, NoLock, Preserve)
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{
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Offset(0x5A),
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, 6,
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PDS, 1, /* 6, Presence detect Change */
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Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
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, 2,
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L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
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L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
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Offset(0xF4), /* BLKPLLEN */
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, 10,
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BPLL, 1,
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}
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OperationRegion (PX02, PCI_Config, 0x338, 0x4)
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Field (PX02, AnyAcc, NoLock, Preserve)
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{
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, 26,
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BDQA, 1 /* BLKDQDA */
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}
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PowerResource (PXP, 0, 0)
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{
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/* Define the PowerResource for PCIe slot */
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Method (_STA, 0, Serialized)
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{
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Store (PDS, PDST)
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If (LEqual (PDS, 1)) {
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Return (0xf)
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} Else {
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Return (0)
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}
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}
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Method (_ON, 0, Serialized)
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{
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* Enter this condition if device
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* is connected
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*/
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/* De-assert PERST */
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\_SB.PCI0.PRDA (\PRT0)
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Store (0, BDQA) /* Set BLKDQDA to 0 */
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Store (0, BPLL) /* Set BLKPLLEN to 0 */
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/* Set L23_Rdy to Detect Transition
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* (L23R2DT)
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*/
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Store (1, L23R)
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Sleep (16)
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Store (0, Local0)
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/* Delay for transition Detect
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* and link to train
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*/
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While (L23R) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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} /* End PDS condition check */
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}
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Method (_OFF, 0, Serialized)
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{
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/* Set L23_Rdy Entry Request (L23ER) */
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If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
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/* enter this condition if device
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* is connected
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*/
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Store (1, L23E)
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Sleep (16)
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Store (0, Local0)
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While (L23E) {
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If (Lgreater (Local0, 4)) {
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Break
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}
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Sleep (16)
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Increment (Local0)
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}
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Store (1, BDQA) /* Set BLKDQDA to 1 */
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Store (1, BPLL) /* Set BLKPLLEN to 1 */
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/* Assert PERST */
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\_SB.PCI0.PRAS (\PRT0)
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} /* End PDS condition check */
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} /* End of Method_OFF */
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} /* End PXP */
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Name(_PR0, Package() { PXP })
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Name(_PR3, Package() { PXP })
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