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mb/intel/ehlcrb: Adjust TSN GBE settings in devicetree 

Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN
ports.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Lean Sheng Tan 2022-05-18 17:58:39 +02:00 committed by Felix Held
parent 823b7b38e8
commit 79fe6a9537
1 changed files with 4 additions and 1 deletions
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5
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
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@ -153,8 +153,11 @@ chip soc/intel/elkhartlake
}" }"
# TSN GBE related UPDs # TSN GBE related UPDs
register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
register "PchTsnGbeSgmiiEnable" = "1" register "PchTsnGbeSgmiiEnable" = "1"
register "PchTsnGbeMultiVcEnable" = "1"
register "PseTsnGbeMultiVcEnable[0]" = "1"
register "PseTsnGbeMultiVcEnable[1]" = "1"
# GPIO for SD card detect # GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5" register "sdcard_cd_gpio" = "GPP_G5"