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soc/intel/tgl/pcie_rp: add TGL-H support 

Add TGL-H support for the recently introduced code for differentiating
CPU and PCH root ports by adding the missing TGL-H port map.

Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2022-01-09 02:17:30 +01:00 committed by Paul Fagerburg
parent c14ba95beb
commit 7a2bc06b12
2 changed files with 21 additions and 1 deletions
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3
src/soc/intel/common/block/include/intelblocks/pcie_rp.h
View File

@ -111,6 +111,9 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
*/
uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
/* Get PCH root port groups */
const struct pcie_rp_group *soc_get_pch_rp_groups(void);
enum pcie_rp_type {
PCIE_RP_UNKNOWN,
PCIE_RP_CPU,

19
src/soc/intel/tigerlake/pcie_rp.c
View File

@ -12,6 +12,13 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
{ .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
{ 0 }
};
static const struct pcie_rp_group cpu_rp_groups[] = {
{ .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3 },
{ .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1 },
@ -40,9 +47,19 @@ static bool is_part_of_group(const struct device *dev,
return false;
}
const struct pcie_rp_group *soc_get_pch_rp_groups(void)
{
if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
return pch_h_rp_groups;
else
return pch_lp_rp_groups;
}
enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
{
if (is_part_of_group(dev, pch_lp_rp_groups))
const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups();
if (is_part_of_group(dev, pch_rp_groups))
return PCIE_RP_PCH;
if (is_part_of_group(dev, cpu_rp_groups))