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soc/intel/alderlake: Remove menu option for MAX_PCIE_CLOCK_SRC 

MAX_PCIE_CLOCK_SRC is not an user-configurable option.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cliff Huang 2022-06-21 09:43:20 -07:00 committed by Felix Held
parent 88f863cfbb
commit 7b4643f5fa
1 changed files with 0 additions and 1 deletions
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src/soc/intel/alderlake/Kconfig
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@ -242,7 +242,6 @@ config MAX_ROOT_PORTS
default MAX_PCH_ROOT_PORTS default MAX_PCH_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC config MAX_PCIE_CLOCK_SRC
prompt "Number of Source Clock supported from SOC"
int int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 5 if SOC_INTEL_ALDERLAKE_PCH_N