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soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin 

`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.

Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-09-22 16:46:16 +05:30
parent cdad2ce2b0
commit 7b523a4be9
1 changed files with 4 additions and 2 deletions
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6
src/soc/intel/alderlake/fsp_params.c
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@ -3,6 +3,7 @@
#include <assert.h>
#include <cbfs.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@ -340,11 +341,12 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
size_t microcode_len;
/* Locate microcode and pass to FSP-S for 2nd microcode loading */
microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
microcode_file = intel_microcode_find();
microcode_len = get_microcode_size(microcode_file);
if ((microcode_file != NULL) && (microcode_len != 0)) {
/* Update CPU Microcode patch base address/size */
s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file;
s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file;
s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
}