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mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0 

This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the brya0 mainboard.

TEST=snippet from dmesg logs shows the correct resources being allocated:
   PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24
   PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20
   PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24
   PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20
   PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24
   PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-03-12 11:51:31 -07:00 committed by Patrick Georgi
parent 8d11cdc6fa
commit 7b97289d56
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig.name
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@ -3,3 +3,4 @@ config BOARD_GOOGLE_BRYA0
select BOARD_GOOGLE_BASEBOARD_BRYA
select BASEBOARD_BRYA_LAPTOP
select BOARD_ROMSIZE_KB_32768
select ADL_ENABLE_USB4_PCIE_RESOURCES