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Move K8_ALLOCATE_IO_RANGE to Kconfig. 

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-07 18:20:51 +00:00 committed by Patrick Georgi
parent 2210135468
commit 7bbd7f2318
27 changed files with 19 additions and 52 deletions
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3
src/mainboard/amd/serengeti_cheetah/romstage.c
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@ -1,8 +1,5 @@
#define SET_NB_CFG_54 1
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0

1
src/mainboard/gigabyte/ga_2761gxdk/Kconfig
View File

@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -21,9 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/gigabyte/m57sli/Kconfig
View File

@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/hp/dl145_g3/Kconfig
View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select RAMINIT_SYSINFO
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -25,9 +25,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

3
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -1,8 +1,5 @@
#define SET_NB_CFG_54 1
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0

3
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -1,8 +1,5 @@
#define SET_NB_CFG_54 1
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0

3
src/mainboard/iwill/dk8x/romstage.c
View File

@ -1,8 +1,5 @@
#define SET_NB_CFG_54 1
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define SET_FIDVID 0
//if we want to wait for core1 done before DQS training, set it to 0

1
src/mainboard/msi/ms7260/Kconfig
View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

1
src/mainboard/msi/ms7260/romstage.c
View File

@ -24,7 +24,6 @@
// #define DQS_TRAIN_DEBUG 1
// #define RES_DEBUG 1
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS == 1
#define SET_NB_CFG_54 1
#endif

3
src/mainboard/msi/ms9185/romstage.c
View File

@ -25,9 +25,6 @@
#define SET_NB_CFG_54 1
//used by incoherent_ht
//#define K8_ALLOCATE_IO_RANGE 1
//used by init_cpus and fidvid
#define SET_FIDVID 1
//if we want to wait for core1 done before DQS training, set it to 0

1
src/mainboard/nvidia/l1_2pvv/Kconfig
View File

@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/sunw/ultra40/Kconfig
View File

@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CK804_USE_NIC
select CK804_USE_ACI
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/sunw/ultra40/romstage.c
View File

@ -1,6 +1,3 @@
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/supermicro/h8dme/Kconfig
View File

@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -16,9 +16,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/supermicro/h8dmr/Kconfig
View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_1024
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/tyan/s2895/Kconfig
View File

@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/tyan/s2895/romstage.c
View File

@ -1,6 +1,3 @@
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

1
src/mainboard/tyan/s2912/Kconfig
View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select QRANK_DIMM_SUPPORT
select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR
string

3
src/mainboard/tyan/s2912/romstage.c
View File

@ -19,9 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define K8_ALLOCATE_IO_RANGE 1
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#endif

4
src/northbridge/amd/amdk8/Kconfig
View File

@ -53,6 +53,10 @@ config QRANK_DIMM_SUPPORT
bool
default n
config K8_ALLOCATE_IO_RANGE
bool
default n
if K8_REV_F_SUPPORT
config DIMM_DDR2

14
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -11,10 +11,6 @@
#define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
#endif
#ifndef K8_ALLOCATE_IO_RANGE
#define K8_ALLOCATE_IO_RANGE 0
#endif
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
@ -720,7 +716,7 @@ static int ht_setup_chains_x(void)
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
#if K8_ALLOCATE_IO_RANGE == 1
#if CONFIG_K8_ALLOCATE_IO_RANGE
unsigned next_io_base;
#endif
@ -740,7 +736,7 @@ static int ht_setup_chains_x(void)
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
#if K8_ALLOCATE_IO_RANGE == 1
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
@ -753,7 +749,7 @@ static int ht_setup_chains_x(void)
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if K8_ALLOCATE_IO_RANGE == 1
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
@ -786,7 +782,7 @@ static int ht_setup_chains_x(void)
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
#if K8_ALLOCATE_IO_RANGE == 1
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
@ -810,7 +806,7 @@ static int ht_setup_chains_x(void)
pci_write_config32(dev, regpos, reg);
}
#if K8_ALLOCATE_IO_RANGE == 1
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
for(i = 0; i< 4; i++) {
unsigned regpos;