soc/intel/common/block: Move tco common functions into block/smbus
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
parent
e7184b0ad0
commit
7bc4dc5648
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@ -93,6 +93,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_TCO
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XDCI
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select SOC_INTEL_COMMON_BLOCK_XHCI
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2016-2018 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -25,6 +25,7 @@
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#include <intelblocks/rtc.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/uart.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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@ -87,8 +88,6 @@ static void enable_pmcbar(void)
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void bootblock_soc_early_init(void)
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{
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uint32_t reg;
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enable_pmcbar();
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/* Clear global reset promotion bit */
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@ -110,10 +109,8 @@ void bootblock_soc_early_init(void)
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/* Initialize GPE for use as interrupt status */
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pmc_gpe_init();
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/* Stop TCO timer */
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reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
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reg |= TCO_TMR_HLT;
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outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
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/* Program TCO Timer Halt */
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tco_configure();
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/* Use Nx and paging to prevent the frontend from writing back dirty
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* cache-as-ram lines to backing store that doesn't exist when the L1I
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@ -21,6 +21,7 @@
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#include <intelblocks/pmclib.h>
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#include <soc/pm.h>
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#include <soc/pci_devs.h>
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#include <soc/smbus.h>
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#include <stdint.h>
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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@ -80,7 +81,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
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/* TCO Timeout */
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if (ps->prev_sleep_state != ACPI_S3 &&
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ps->tco_sts & TCO_TIMEOUT)
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ps->tco1_sts & TCO_TIMEOUT)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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@ -29,6 +29,9 @@
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#define ACPI_BASE_SIZE 0x100
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#define R_ACPI_PM1_TMR 0x8
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#define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60)
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#define TCO_BASE_SIZE 0x20
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/* CST Range (R/W) IO port block size */
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#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5
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/* ACPI PMIO Offset to C-state register*/
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@ -40,5 +40,6 @@
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#define PID_TUNIT 0x52
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#define PID_PSF3 0xC6
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#define PID_DMI 0x00 /* Reserved */
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#endif /* SOC_INTEL_APL_PCR_H */
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@ -131,10 +131,6 @@
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#define GPE_CNTL 0x50
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#define DEVACT_STS 0x4c
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#define TCO_STS 0x64
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#define TCO_TIMEOUT (1 << 3)
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#define TCO1_CNT 0x68
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#define TCO_TMR_HLT (1 << 11)
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#define GPE0_REG_MAX 4
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#define GPE0_REG_SIZE 32
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@ -240,7 +236,8 @@ struct chipset_power_state {
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uint32_t pm1_cnt;
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uint32_t gpe0_sts[GPE0_REG_MAX];
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uint32_t gpe0_en[GPE0_REG_MAX];
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uint32_t tco_sts;
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uint16_t tco1_sts;
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uint16_t tco2_sts;
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uint32_t prsts;
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uint32_t gen_pmcon1;
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uint32_t gen_pmcon2;
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_SMBUS_H_
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#define _SOC_APOLLOLAKE_SMBUS_H_
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/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#endif
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@ -28,11 +28,13 @@
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#include <intelblocks/msr.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/tco.h>
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#include <rules.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <timer.h>
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#include <security/vboot/vbnv.h>
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#include "chip.h"
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@ -133,15 +135,6 @@ const char *const *soc_std_gpe_sts_array(size_t *a)
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return gpe_sts_bits;
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}
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uint32_t soc_reset_tco_status(void)
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{
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uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
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uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
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outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);
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return tco_sts & tco_en;
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}
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void soc_clear_pm_registers(uintptr_t pmc_bar)
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{
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uint32_t gen_pmcon1;
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@ -173,14 +166,18 @@ void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uintptr_t pmc_bar0 = read_pmc_mmio_bar();
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ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
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ps->tco1_sts = tco_read_reg(TCO1_STS);
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ps->tco2_sts = tco_read_reg(TCO2_STS);
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ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
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ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
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ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
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ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
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printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
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ps->prsts, ps->tco_sts);
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printk(BIOS_DEBUG, "prsts: %08x\n",
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ps->prsts);
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printk(BIOS_DEBUG, "tco_sts: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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printk(BIOS_DEBUG,
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"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
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ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -24,6 +24,7 @@
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/smbus.h>
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#include <intelblocks/tco.h>
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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@ -52,8 +53,6 @@
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#define PCR_DMI_ACPIBDID 0x27B8
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#define PCR_DMI_PMBASEA 0x27AC
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#define PCR_DMI_PMBASEC 0x27B0
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#define PCR_DMI_TCOBASE 0x2778
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#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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@ -141,35 +140,6 @@ static void soc_config_acpibase(void)
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}
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}
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static void soc_config_tco(void)
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{
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uint32_t reg32;
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uint16_t tcobase;
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uint16_t tcocnt;
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/* Disable TCO in SMBUS Device first before changing Base Address */
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reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
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reg32 &= ~TCO_BASE_EN;
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pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
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/* Program TCO Base */
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tcobase = TCO_BASE_ADDRESS;
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pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);
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/* Enable TCO in SMBUS */
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pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);
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/*
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* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
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*/
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pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
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/* Program TCO timer halt */
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tcocnt = inw(tcobase + TCO1_CNT);
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tcocnt |= TCO_TMR_HLT;
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outw(tcocnt, tcobase + TCO1_CNT);
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}
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static int pch_check_decode_enable(void)
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{
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uint32_t dmi_control;
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@ -216,7 +186,7 @@ void pch_early_init(void)
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soc_config_acpibase();
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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soc_config_tco();
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tco_configure();
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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smbus_common_init();
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@ -23,6 +23,7 @@
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/tco.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <soc/p2sb.h>
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@ -55,17 +56,11 @@ static void pch_finalize(void)
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{
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struct device *dev;
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uint32_t reg32;
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uint16_t tcobase, tcocnt;
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uint8_t *pmcbase;
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config_t *config;
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uint8_t reg8;
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/* TCO Lock down */
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tcobase = smbus_tco_regs();
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tcocnt = inw(tcobase + TCO1_CNT);
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tcocnt |= TCO_LOCK;
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outw(tcocnt, tcobase + TCO1_CNT);
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tco_lockdown();
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/*
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* Disable ACPI PM timer based on dt policy
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*
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@ -4,7 +4,7 @@
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,11 +19,6 @@
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#ifndef _SOC_CANNONLAKE_SMBUS_H_
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#define _SOC_CANNONLAKE_SMBUS_H_
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/* PCI registers */
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#define TCOBASE 0x50 /* TCO base address. */
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#define TCOCTL 0x54
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#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
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/* IO and MMIO registers under primary BAR */
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/* Set address for PCH as SMBus slave role */
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#define SMB_RCV_SLVA 0x09
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@ -32,10 +27,10 @@
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#define TCO1_STS 0x04
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#define TCO_TIMEOUT (1 << 3)
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#define TCO2_STS 0x06
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define TCO_STS_SECOND_TO (1 << 1)
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#define TCO1_CNT 0x08
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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#define TCO_LOCK (1 << 12)
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#define TCO_TMR_HLT (1 << 11)
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/*
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* Default slave address value for PCH. This value is set to match default
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@ -29,6 +29,7 @@
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#include <console/console.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/tco.h>
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#include <halt.h>
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#include <rules.h>
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#include <stdlib.h>
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@ -154,38 +155,6 @@ uint8_t *pmc_mmio_regs(void)
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return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
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}
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uint16_t smbus_tco_regs(void)
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{
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uint16_t reg16;
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reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
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return ALIGN_DOWN(reg16, 0x20);
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}
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uint32_t soc_reset_tco_status(void)
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{
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u16 tco1_sts;
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u16 tco2_sts;
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u16 tcobase;
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tcobase = smbus_tco_regs();
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/* TCO Status 2 register */
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tco2_sts = inw(tcobase + TCO2_STS);
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tco2_sts |= TCO2_STS_SECOND_TO;
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outw(tco2_sts, tcobase + TCO2_STS);
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/* TCO Status 1 register */
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tco1_sts = inw(tcobase + TCO1_STS);
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/* Clear SECOND_TO_STS bit */
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if (tco2_sts & TCO2_STS_SECOND_TO)
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outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
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return (tco2_sts << 16) | tco1_sts;
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}
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t)pmc_mmio_regs();
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@ -19,6 +19,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/tco.h>
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#include <string.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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@ -66,13 +67,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
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void soc_fill_power_state(struct chipset_power_state *ps)
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{
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uint16_t tcobase;
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uint8_t *pmc;
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tcobase = smbus_tco_regs();
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ps->tco1_sts = inw(tcobase + TCO1_STS);
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ps->tco2_sts = inw(tcobase + TCO2_STS);
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ps->tco1_sts = tco_read_reg(TCO1_STS);
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ps->tco2_sts = tco_read_reg(TCO2_STS);
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printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
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ps->tco1_sts, ps->tco2_sts);
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@ -93,13 +93,6 @@ uint32_t pmc_clear_tco_status(void);
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*/
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const char *const *soc_tco_sts_array(size_t *a);
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/*
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* Resets the tco status registers. This function clears the tco_sts register
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* and returns the sts and enable bits set.
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*/
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uint32_t soc_reset_tco_status(void);
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/* GPE */
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/*
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@ -0,0 +1,36 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOC_INTEL_COMMON_BLOCK_TCO_H
|
||||
#define SOC_INTEL_COMMON_BLOCK_TCO_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Enable TCO BAR using SMBUS TCO base to access TCO related register
|
||||
* also disable the timer.
|
||||
*/
|
||||
void tco_configure(void);
|
||||
/* Lockdown TCO registers before booting to OS */
|
||||
void tco_lockdown(void);
|
||||
/*
|
||||
* Resets the tco status registers. This function clears the tco_sts register
|
||||
* and returns the status bits set.
|
||||
*/
|
||||
uint32_t tco_reset_status(void);
|
||||
uint16_t tco_read_reg(uint16_t tco_reg);
|
||||
void tco_write_reg(uint16_t tco_reg, uint16_t value);
|
||||
|
||||
#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */
|
|
@ -20,6 +20,7 @@
|
|||
#include <halt.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/gpio.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <soc/pm.h>
|
||||
#include <string.h>
|
||||
#include <timer.h>
|
||||
|
@ -260,7 +261,7 @@ static uint32_t print_tco_status(uint32_t tco_sts)
|
|||
|
||||
uint32_t pmc_clear_tco_status(void)
|
||||
{
|
||||
return print_tco_status(soc_reset_tco_status());
|
||||
return print_tco_status(tco_reset_status());
|
||||
}
|
||||
|
||||
/* GPE */
|
||||
|
|
|
@ -2,3 +2,14 @@ config SOC_INTEL_COMMON_BLOCK_SMBUS
|
|||
bool
|
||||
help
|
||||
Intel Processor common SMBus support
|
||||
|
||||
config SOC_INTEL_COMMON_BLOCK_TCO
|
||||
bool
|
||||
help
|
||||
Intel Processor common TCO support
|
||||
|
||||
config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS
|
||||
bool
|
||||
depends on SOC_INTEL_COMMON_BLOCK_TCO
|
||||
help
|
||||
Select this config to enable TCO BAR through SMBUS
|
||||
|
|
|
@ -1,8 +1,15 @@
|
|||
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
|
||||
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
|
||||
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
|
||||
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
|
||||
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
|
||||
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
|
||||
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
|
||||
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c
|
||||
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
|
||||
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
|
||||
|
|
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smbus.h>
|
||||
|
||||
#define PCR_DMI_TCOBASE 0x2778
|
||||
/* Enable TCO I/O range decode. */
|
||||
#define TCOEN (1 << 1)
|
||||
|
||||
/* SMBUS TCO base address. */
|
||||
#define TCOBASE 0x50
|
||||
#define TCOCTL 0x54
|
||||
#define TCO_BASE_EN (1 << 8)
|
||||
|
||||
/* Get base address of TCO I/O registers. */
|
||||
static uint16_t tco_get_bar(void)
|
||||
{
|
||||
return TCO_BASE_ADDRESS;
|
||||
}
|
||||
|
||||
uint16_t tco_read_reg(uint16_t tco_reg)
|
||||
{
|
||||
uint16_t tcobase;
|
||||
|
||||
tcobase = tco_get_bar();
|
||||
|
||||
return inw(tcobase + tco_reg);
|
||||
}
|
||||
|
||||
void tco_write_reg(uint16_t tco_reg, uint16_t value)
|
||||
{
|
||||
uint16_t tcobase;
|
||||
|
||||
tcobase = tco_get_bar();
|
||||
|
||||
outw(value, tcobase + tco_reg);
|
||||
}
|
||||
|
||||
void tco_lockdown(void)
|
||||
{
|
||||
uint16_t tcocnt;
|
||||
|
||||
/* TCO Lock down */
|
||||
tcocnt = tco_read_reg(TCO1_CNT);
|
||||
tcocnt |= TCO_LOCK;
|
||||
tco_write_reg(TCO1_CNT, tcocnt);
|
||||
}
|
||||
|
||||
uint32_t tco_reset_status(void)
|
||||
{
|
||||
uint16_t tco1_sts;
|
||||
uint16_t tco2_sts;
|
||||
|
||||
/* TCO Status 2 register */
|
||||
tco2_sts = tco_read_reg(TCO2_STS);
|
||||
tco2_sts |= TCO_STS_SECOND_TO;
|
||||
tco_write_reg(TCO2_STS, tco2_sts);
|
||||
|
||||
/* TCO Status 1 register */
|
||||
tco1_sts = tco_read_reg(TCO1_STS);
|
||||
|
||||
return (tco2_sts << 16) | tco1_sts;
|
||||
}
|
||||
|
||||
/* Stop TCO timer */
|
||||
static void tco_timer_disable(void)
|
||||
{
|
||||
uint16_t tcocnt;
|
||||
|
||||
/* Program TCO timer halt */
|
||||
tcocnt = tco_read_reg(TCO1_CNT);
|
||||
tcocnt |= TCO_TMR_HLT;
|
||||
tco_write_reg(TCO1_CNT, tcocnt);
|
||||
}
|
||||
|
||||
/* Enable TCO BAR using SMBUS TCO base to access TCO related register */
|
||||
static void tco_enable_bar(void)
|
||||
{
|
||||
uint32_t reg32;
|
||||
uint16_t tcobase;
|
||||
#if defined(__SIMPLE_DEVICE__)
|
||||
int devfn = PCH_DEVFN_SMBUS;
|
||||
pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
|
||||
#else
|
||||
struct device *dev;
|
||||
dev = PCH_DEV_SMBUS;
|
||||
#endif
|
||||
|
||||
/* Disable TCO in SMBUS Device first before changing Base Address */
|
||||
reg32 = pci_read_config32(dev, TCOCTL);
|
||||
reg32 &= ~TCO_BASE_EN;
|
||||
pci_write_config32(dev, TCOCTL, reg32);
|
||||
|
||||
/* Program TCO Base */
|
||||
tcobase = tco_get_bar();
|
||||
pci_write_config32(dev, TCOBASE, tcobase);
|
||||
|
||||
/* Enable TCO in SMBUS */
|
||||
pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN);
|
||||
|
||||
/*
|
||||
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
|
||||
*/
|
||||
pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable TCO BAR using SMBUS TCO base to access TCO related register
|
||||
* also disable the timer.
|
||||
*/
|
||||
void tco_configure(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS))
|
||||
tco_enable_bar();
|
||||
|
||||
tco_timer_disable();
|
||||
}
|
|
@ -31,6 +31,7 @@
|
|||
#include <soc/pm.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/smbus.h>
|
||||
#include <spi-generic.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
|
|
@ -37,6 +37,8 @@ config PCH_SPECIFIC_OPTIONS
|
|||
select SOC_INTEL_COMMON_BLOCK_SCS
|
||||
select SOC_INTEL_COMMON_BLOCK_SMBUS
|
||||
select SOC_INTEL_COMMON_BLOCK_SPI
|
||||
select SOC_INTEL_COMMON_BLOCK_TCO
|
||||
select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS
|
||||
select SOC_INTEL_COMMON_BLOCK_TIMER
|
||||
select SOC_INTEL_COMMON_BLOCK_UART
|
||||
select SOC_INTEL_COMMON_BLOCK_XDCI
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/rtc.h>
|
||||
#include <intelblocks/smbus.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <soc/bootblock.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/lpc.h>
|
||||
|
@ -49,9 +50,6 @@
|
|||
#define PCR_DMI_ACPIBDID 0x27B8
|
||||
#define PCR_DMI_PMBASEA 0x27AC
|
||||
#define PCR_DMI_PMBASEC 0x27B0
|
||||
#define PCR_DMI_TCOBASE 0x2778
|
||||
/* Enable TCO I/O range decode. */
|
||||
#define TCOEN (1 << 1)
|
||||
|
||||
#define PCR_DMI_LPCIOD 0x2770
|
||||
#define PCR_DMI_LPCIOE 0x2774
|
||||
|
@ -119,35 +117,6 @@ static void soc_config_acpibase(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void soc_config_tco(void)
|
||||
{
|
||||
uint32_t reg32;
|
||||
uint16_t tcobase;
|
||||
uint16_t tcocnt;
|
||||
|
||||
/* Disable TCO in SMBUS Device first before changing Base Address */
|
||||
reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
|
||||
reg32 &= ~TCO_BASE_EN;
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
|
||||
|
||||
/* Program TCO Base */
|
||||
tcobase = TCO_BASE_ADDRESS;
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);
|
||||
|
||||
/* Enable TCO in SMBUS */
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);
|
||||
|
||||
/*
|
||||
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
|
||||
*/
|
||||
pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
|
||||
|
||||
/* Program TCO timer halt */
|
||||
tcocnt = inw(tcobase + TCO1_CNT);
|
||||
tcocnt |= TCO_TMR_HLT;
|
||||
outw(tcocnt, tcobase + TCO1_CNT);
|
||||
}
|
||||
|
||||
static int pch_check_decode_enable(void)
|
||||
{
|
||||
uint32_t dmi_control;
|
||||
|
@ -194,7 +163,7 @@ void pch_early_init(void)
|
|||
soc_config_acpibase();
|
||||
|
||||
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
|
||||
soc_config_tco();
|
||||
tco_configure();
|
||||
|
||||
/* Program SMBUS_BASE_ADDRESS and Enable it */
|
||||
smbus_common_init();
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <intelblocks/lpc_lib.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <reg_script.h>
|
||||
#include <spi-generic.h>
|
||||
#include <soc/p2sb.h>
|
||||
|
@ -54,16 +55,12 @@ static void pch_finalize(void)
|
|||
{
|
||||
struct device *dev;
|
||||
uint32_t reg32;
|
||||
uint16_t tcobase, tcocnt;
|
||||
uint8_t *pmcbase;
|
||||
config_t *config;
|
||||
uint8_t reg8;
|
||||
|
||||
/* TCO Lock down */
|
||||
tcobase = smbus_tco_regs();
|
||||
tcocnt = inw(tcobase + TCO1_CNT);
|
||||
tcocnt |= TCO_LOCK;
|
||||
outw(tcocnt, tcobase + TCO1_CNT);
|
||||
tco_lockdown();
|
||||
|
||||
/*
|
||||
* Disable ACPI PM timer based on dt policy
|
||||
|
|
|
@ -16,11 +16,6 @@
|
|||
#ifndef _SOC_ICELAKE_SMBUS_H_
|
||||
#define _SOC_ICELAKE_SMBUS_H_
|
||||
|
||||
/* PCI registers */
|
||||
#define TCOBASE 0x50 /* TCO base address. */
|
||||
#define TCOCTL 0x54
|
||||
#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
|
||||
|
||||
/* IO and MMIO registers under primary BAR */
|
||||
/* Set address for PCH as SMBus slave role */
|
||||
#define SMB_RCV_SLVA 0x09
|
||||
|
@ -29,10 +24,10 @@
|
|||
#define TCO1_STS 0x04
|
||||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO2_STS_SECOND_TO (1 << 1)
|
||||
#define TCO_STS_SECOND_TO (1 << 1)
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
|
||||
/*
|
||||
* Default slave address value for PCH. This value is set to match default
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <console/console.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/rtc.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <halt.h>
|
||||
#include <rules.h>
|
||||
#include <stdlib.h>
|
||||
|
@ -153,38 +154,6 @@ uint8_t *pmc_mmio_regs(void)
|
|||
return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
|
||||
}
|
||||
|
||||
uint16_t smbus_tco_regs(void)
|
||||
{
|
||||
uint16_t reg16;
|
||||
|
||||
reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
|
||||
|
||||
return ALIGN_DOWN(reg16, 0x20);
|
||||
}
|
||||
|
||||
uint32_t soc_reset_tco_status(void)
|
||||
{
|
||||
u16 tco1_sts;
|
||||
u16 tco2_sts;
|
||||
u16 tcobase;
|
||||
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
/* TCO Status 2 register */
|
||||
tco2_sts = inw(tcobase + TCO2_STS);
|
||||
tco2_sts |= TCO2_STS_SECOND_TO;
|
||||
outw(tco2_sts, tcobase + TCO2_STS);
|
||||
|
||||
/* TCO Status 1 register */
|
||||
tco1_sts = inw(tcobase + TCO1_STS);
|
||||
|
||||
/* Clear SECOND_TO_STS bit */
|
||||
if (tco2_sts & TCO2_STS_SECOND_TO)
|
||||
outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
|
||||
|
||||
return (tco2_sts << 16) | tco1_sts;
|
||||
}
|
||||
|
||||
uintptr_t soc_read_pmc_base(void)
|
||||
{
|
||||
return (uintptr_t)pmc_mmio_regs();
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <string.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
|
@ -65,13 +66,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
|
|||
|
||||
void soc_fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
uint16_t tcobase;
|
||||
uint8_t *pmc;
|
||||
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
ps->tco1_sts = inw(tcobase + TCO1_STS);
|
||||
ps->tco2_sts = inw(tcobase + TCO2_STS);
|
||||
ps->tco1_sts = tco_read_reg(TCO1_STS);
|
||||
ps->tco2_sts = tco_read_reg(TCO2_STS);
|
||||
|
||||
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
|
||||
ps->tco1_sts, ps->tco2_sts);
|
||||
|
|
|
@ -2,8 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
* Copyright (C) 2015-2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -27,6 +26,7 @@
|
|||
#include <intelblocks/pmclib.h>
|
||||
#include <intelblocks/rtc.h>
|
||||
#include <intelblocks/smbus.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <soc/bootblock.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/p2sb.h>
|
||||
|
@ -43,7 +43,6 @@
|
|||
#define PCR_DMI_ACPIBDID 0x27B8
|
||||
#define PCR_DMI_PMBASEA 0x27AC
|
||||
#define PCR_DMI_PMBASEC 0x27B0
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||||
#define PCR_DMI_TCOBASE 0x2778
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||||
|
||||
void bootblock_pch_early_init(void)
|
||||
{
|
||||
|
@ -112,37 +111,6 @@ static void soc_config_pwrmbase(void)
|
|||
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
|
||||
}
|
||||
|
||||
static void soc_config_tco(void)
|
||||
{
|
||||
uint32_t reg32 = 0;
|
||||
uint16_t tcobase;
|
||||
uint16_t tcocnt;
|
||||
|
||||
/* Disable TCO in SMBUS Device first before changing Base Address */
|
||||
reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
|
||||
reg32 &= ~TCO_EN;
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
|
||||
|
||||
/* Program TCO Base */
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDRESS);
|
||||
|
||||
/* Enable TCO in SMBUS */
|
||||
pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
|
||||
|
||||
/*
|
||||
* Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
|
||||
* to [SMBUS PCI offset 50h[15:5], 1].
|
||||
*/
|
||||
pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDRESS | (1 << 1));
|
||||
|
||||
/* Program TCO timer halt */
|
||||
tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
|
||||
tcobase &= ~0x1f;
|
||||
tcocnt = inw(tcobase + TCO1_CNT);
|
||||
tcocnt |= TCO_TMR_HLT;
|
||||
outw(tcocnt, tcobase + TCO1_CNT);
|
||||
}
|
||||
|
||||
static int pch_check_decode_enable(void)
|
||||
{
|
||||
uint32_t dmi_control;
|
||||
|
@ -196,7 +164,7 @@ void pch_early_init(void)
|
|||
soc_config_pwrmbase();
|
||||
|
||||
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
|
||||
soc_config_tco();
|
||||
tco_configure();
|
||||
|
||||
/* Program SMBUS_BASE_ADDRESS and Enable it */
|
||||
smbus_common_init();
|
||||
|
|
|
@ -373,7 +373,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
|
|||
|
||||
/* TCO Timeout */
|
||||
if (ps->prev_sleep_state != ACPI_S3 &&
|
||||
ps->tco2_sts & TCO2_STS_SECOND_TO)
|
||||
ps->tco2_sts & TCO_STS_SECOND_TO)
|
||||
elog_add_event(ELOG_TYPE_TCO_RESET);
|
||||
|
||||
/* Power Button Override */
|
||||
|
|
|
@ -183,9 +183,6 @@ int acpi_sci_irq(void);
|
|||
/* Get base address PMC memory mapped registers. */
|
||||
uint8_t *pmc_mmio_regs(void);
|
||||
|
||||
/* Get base address of TCO I/O registers. */
|
||||
uint16_t smbus_tco_regs(void);
|
||||
|
||||
/* Set the DISB after DRAM init */
|
||||
void pmc_set_disb(void);
|
||||
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
|
||||
* Copyright (C) 2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015-2017 Intel Corporation.
|
||||
* Copyright (C) 2015-2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -22,20 +22,14 @@
|
|||
/* PCI Configuration Space (D31:F3): SMBus */
|
||||
#define SMB_RCV_SLVA 0x09
|
||||
|
||||
/* SMBUS TCO base address. */
|
||||
#define TCOBASE 0x50
|
||||
#define TCOCTL 0x54
|
||||
#define TCO_EN (1 << 8)
|
||||
|
||||
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
|
||||
#define TCO1_STS 0x04
|
||||
#define TCO_TIMEOUT (1 << 3)
|
||||
#define TCO2_STS 0x06
|
||||
#define TCO2_STS_SECOND_TO 0x02
|
||||
#define TCO2_STS_BOOT 0x04
|
||||
#define TCO_STS_SECOND_TO 0x02
|
||||
#define TCO1_CNT 0x08
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
#define TCO_LOCK (1 << 12)
|
||||
#define TCO_TMR_HLT (1 << 11)
|
||||
|
||||
/* SMBus I/O bits. */
|
||||
#define SMBUS_SLAVE_ADDR 0x24
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <intelblocks/pmclib.h>
|
||||
#include <halt.h>
|
||||
#include <intelblocks/lpc_lib.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <rules.h>
|
||||
#include <stdlib.h>
|
||||
#include <soc/gpe.h>
|
||||
|
@ -168,40 +169,6 @@ uint8_t *pmc_mmio_regs(void)
|
|||
return (void *)(uintptr_t) reg32;
|
||||
}
|
||||
|
||||
uint16_t smbus_tco_regs(void)
|
||||
{
|
||||
uint16_t reg16;
|
||||
|
||||
reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
|
||||
|
||||
reg16 &= ~0x1f;
|
||||
|
||||
return reg16;
|
||||
}
|
||||
|
||||
uint32_t soc_reset_tco_status(void)
|
||||
{
|
||||
u16 tco1_sts;
|
||||
u16 tco2_sts;
|
||||
u16 tcobase;
|
||||
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
/* TCO Status 2 register */
|
||||
tco2_sts = inw(tcobase + TCO2_STS);
|
||||
tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
|
||||
outw(tco2_sts, tcobase + TCO2_STS);
|
||||
|
||||
/* TCO Status 1 register */
|
||||
tco1_sts = inw(tcobase + TCO1_STS);
|
||||
|
||||
/* Clear SECOND_TO_STS bit */
|
||||
if (tco2_sts & TCO2_STS_SECOND_TO)
|
||||
outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
|
||||
|
||||
return (tco2_sts << 16) | tco1_sts;
|
||||
}
|
||||
|
||||
uintptr_t soc_read_pmc_base(void)
|
||||
{
|
||||
return (uintptr_t) (pmc_mmio_regs());
|
||||
|
@ -285,13 +252,10 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
|
|||
|
||||
void soc_fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
uint16_t tcobase;
|
||||
uint8_t *pmc;
|
||||
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
ps->tco1_sts = inw(tcobase + TCO1_STS);
|
||||
ps->tco2_sts = inw(tcobase + TCO2_STS);
|
||||
ps->tco1_sts = tco_read_reg(TCO1_STS);
|
||||
ps->tco2_sts = tco_read_reg(TCO2_STS);
|
||||
|
||||
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
|
||||
ps->tco1_sts, ps->tco2_sts);
|
||||
|
|
Loading…
Reference in New Issue