mainboard/google: Update the TLMM registers for sdhc
Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57450 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -6,15 +6,25 @@
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#include <soc/clock.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <bootblock_common.h>
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#include <soc/clock.h>
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static void configure_sdhci(void)
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{
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/* Program eMMC drive strength to 16/10/10 mA */
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write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
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/* Program SD card drive strength to 16/10/10 mA */
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write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4);
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}
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static void mainboard_init(struct device *dev)
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{
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/* Configure clock for eMMC */
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clock_configure_sdcc(1, 384 * MHz);
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/* Configure clock for SD card */
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clock_configure_sdcc(2, 50 * MHz);
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configure_sdhci();
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}
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static void mainboard_enable(struct device *dev)
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@ -1,8 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/mmio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/usb.h>
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#include <soc/addressmap.h>
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static struct usb_board_data usb1_board_data = {
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.parameter_override_x0 = 0x63,
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@ -17,6 +19,12 @@ static void setup_usb(void)
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setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data);
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}
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static void configure_sdhci(void)
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{
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/* Program eMMC drive strength to 16/10/10 mA */
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write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
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}
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static void mainboard_init(struct device *dev)
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{
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/* Copy WIFI calibration data into CBMEM. */
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@ -24,6 +32,7 @@ static void mainboard_init(struct device *dev)
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cbmem_add_vpd_calibration_data();
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setup_usb();
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configure_sdhci();
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}
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static void mainboard_enable(struct device *dev)
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@ -6,6 +6,7 @@
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c_simple.h>
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#include <device/mmio.h>
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#include <mipi/panel.h>
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#include <drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h>
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#include <edid.h>
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@ -19,6 +20,7 @@
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#include <types.h>
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#include "board.h"
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#include <soc/addressmap.h>
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#define BRIDGE_BUS 0x2
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#define BRIDGE_CHIP 0x2d
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@ -202,6 +204,14 @@ static void display_startup(void)
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}
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}
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static void configure_sdhci(void)
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{
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/* Program eMMC drive strength to 16/16/16 mA */
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write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FFF);
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/* Program SD card drive strength to 16/10/10 mA */
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write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4);
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}
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static void mainboard_init(struct device *dev)
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{
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/* Take FPMCU out of reset. Power was already applied
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@ -213,6 +223,7 @@ static void mainboard_init(struct device *dev)
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qi2s_configure_gpios();
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load_qup_fw();
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display_startup();
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configure_sdhci();
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}
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static void mainboard_enable(struct device *dev)
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@ -9,4 +9,7 @@
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#define TLMM_SOUTH_TILE_BASE 0x1000000
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#define GCC_BASE 0x01800000
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/* SDHC TLMM Registers */
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#define SDC1_TLMM_CFG_ADDR 0x010C2000
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#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */
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@ -56,4 +56,8 @@
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#define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1
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#define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK
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/* SDHC TLMM Registers */
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#define SDC1_TLMM_CFG_ADDR 0x03D7A000
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#define SDC2_TLMM_CFG_ADDR 0x03D7B000
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#endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */
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@ -24,4 +24,8 @@
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#define GPIO_FUNC_QSPI_DATA_1 GPIO13_FUNC_QSPI_DATA_1
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#define GPIO_FUNC_QSPI_CLK GPIO14_FUNC_QSPI_CLK
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/* SDHC TLMM Registers */
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#define SDC1_TLMM_CFG_ADDR 0x0F1B3000
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#define SDC2_TLMM_CFG_ADDR 0x0F1B4000
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#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */
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