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soc/amd/stoneyridge: Clarify BAR mask in SPI base 

The format of the D14F3xA0 SPI Base_Addr register is different
than a traditional BAR.  Change the function to preserve any
enables already in place.  Change the AND mask to remove the
reserved field and the enables.

Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson 2017-07-27 09:05:44 -06:00 committed by Martin Roth
parent 03e44f46b0
commit 7bf860ffed
1 changed files with 6 additions and 3 deletions
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9
src/soc/amd/stoneyridge/early_setup.c
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@ -242,13 +242,16 @@ static uintptr_t hudson_spibase(void)
{
/* Make sure the base address is predictable */
device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
u32 base, enables;
base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
enables = base & 0xf;
base &= ~0x3f;
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
& 0xfffffff0;
if (!base) {
base = SPI_BASE_ADDRESS;
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base
| SPI_ROM_ENABLE);
| enables | SPI_ROM_ENABLE);
/* PCI_COMMAND_MEMORY is read-only and enabled. */
}
return (uintptr_t)base;