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soc/intel/skylake: Clean up the skylake PCH H device ID macros 

Rename the device ID macros as per the skylake PCH H external design
specification.

Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23381
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
V Sowmya 2018-01-23 14:44:45 +05:30 committed by Aaron Durbin
parent cb8123ae48
commit 7c150472df
6 changed files with 19 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/include/device/pci_ids.h
View File

@ -2665,9 +2665,9 @@
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48
#define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46
#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa150
#define PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM 0xa14e
#define PCI_DEVICE_ID_INTEL_KBP_H_QM170 0xa14d
#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150
#define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e
#define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d
#define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22 0x9d4b
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22 0x9d4e
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22 0x9d50
@ -2770,7 +2770,7 @@
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_SPT_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
@ -2809,9 +2809,9 @@
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
#define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28
#define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66
#define PCI_DEVICE_ID_INTEL_KBP_H_UART0 0xa127
#define PCI_DEVICE_ID_INTEL_KBP_H_UART1 0xa128
#define PCI_DEVICE_ID_INTEL_KBP_H_UART2 0xa166
#define PCI_DEVICE_ID_INTEL_SPT_H_UART0 0xa127
#define PCI_DEVICE_ID_INTEL_SPT_H_UART1 0xa128
#define PCI_DEVICE_ID_INTEL_SPT_H_UART2 0xa166
#define PCI_DEVICE_ID_INTEL_APL_UART0 0x5abc
#define PCI_DEVICE_ID_INTEL_APL_UART1 0x5abe
#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0
@ -2889,7 +2889,7 @@
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
#define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8
#define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
/* Intel P2SB device Ids */

6
src/soc/intel/common/block/lpc/lpc.c
View File

@ -124,9 +124,9 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE,
PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM,
PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM,
PCI_DEVICE_ID_INTEL_KBP_H_C236,
PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM,
PCI_DEVICE_ID_INTEL_KBP_H_QM170,
PCI_DEVICE_ID_INTEL_SPT_H_C236,
PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM,
PCI_DEVICE_ID_INTEL_SPT_H_QM170,
PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22,
PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22,
PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22,

2
src/soc/intel/common/block/pmc/pmc.c
View File

@ -105,7 +105,7 @@ static struct device_operations device_ops = {
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_SPT_LP_PMC,
PCI_DEVICE_ID_INTEL_KBP_H_PMC,
PCI_DEVICE_ID_INTEL_SPT_H_PMC,
PCI_DEVICE_ID_INTEL_APL_PMC,
PCI_DEVICE_ID_INTEL_GLK_PMC,
0

6
src/soc/intel/common/block/uart/uart.c
View File

@ -151,9 +151,9 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_SPT_UART0,
PCI_DEVICE_ID_INTEL_SPT_UART1,
PCI_DEVICE_ID_INTEL_SPT_UART2,
PCI_DEVICE_ID_INTEL_KBP_H_UART0,
PCI_DEVICE_ID_INTEL_KBP_H_UART1,
PCI_DEVICE_ID_INTEL_KBP_H_UART2,
PCI_DEVICE_ID_INTEL_SPT_H_UART0,
PCI_DEVICE_ID_INTEL_SPT_H_UART1,
PCI_DEVICE_ID_INTEL_SPT_H_UART2,
PCI_DEVICE_ID_INTEL_APL_UART0,
PCI_DEVICE_ID_INTEL_APL_UART1,
PCI_DEVICE_ID_INTEL_APL_UART2,

2
src/soc/intel/common/block/xhci/xhci.c
View File

@ -35,7 +35,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CNL_LP_XHCI,
PCI_DEVICE_ID_INTEL_GLK_XHCI,
PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
0
};

6
src/soc/intel/skylake/bootblock/report_platform.c
View File

@ -66,9 +66,9 @@ static struct {
{ PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, "Skylake-U Base" },
{ PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, "Skylake-U Premium" },
{ PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_H_PREMIUM, "Kabylake-H Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_H_C236, "Kabylake-H C236" },
{ PCI_DEVICE_ID_INTEL_KBP_H_QM170, "Kabylake-H QM170" },
{ PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" },
{ PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" },
{ PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" },
{ PCI_DEVICE_ID_INTEL_KBP_LP_U_PREMIUM, "Kabylake-U Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM, "Kabylake-Y Premium" },
{ PCI_DEVICE_ID_INTEL_KBP_LP_SUPER_SKU, "Kabylake Super Sku" },