GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4043

Browse source 
Update FSP headers for Tiger Lake platform generated based on FSP
version 4043. Previous version was 3444.

BUG=b:178846052
BRANCH=none
TEST=none

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibada380fe757d9a8b50b2ddfeb2c86b4a98cb5e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Srinidhi N Kaushik 2021-01-29 15:14:25 -08:00 committed by Nick Vaccaro
parent b571846ea4
commit 7c25317093
2 changed files with 7 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -2505,7 +2505,7 @@ typedef struct {
/** Offset 0x091C - Reserved
**/
UINT8 Reserved45[44];
UINT8 Reserved45[52];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@ -2524,11 +2524,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x0948
/** Offset 0x0950
**/
UINT8 UnusedUpdSpace27[6];
UINT8 UnusedUpdSpace28[6];
/** Offset 0x094E
/** Offset 0x0956
**/
UINT16 UpdTerminator;
} FSPM_UPD;

3
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
View file

@ -934,7 +934,8 @@ typedef struct {
UINT8 Reserved20[2];
/** Offset 0x04BC - Disable TC code On USB Connect
Enable(default) or Disable TC cold On Usb Connected
Enable: Unsupported TC cold capability on Usb Connected, Disable(default): Supported
TC cold On Usb Connected
$EN_DIS
**/
UINT8 DisableTccoldOnUsbConnected;