soc/amd/picasso: Move sd_emmc_config into emmc_config struct
I plan on adding another eMMC parameter. This refactor keeps the config contained in a single struct. BUG=b:159823235 TEST=Build test Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
73cd3e704f
commit
7c79d8302b
8 changed files with 42 additions and 22 deletions
|
@ -112,7 +112,7 @@ static void mainboard_init(void *chip_info)
|
||||||
struct soc_amd_picasso_config *cfg = config_of_soc();
|
struct soc_amd_picasso_config *cfg = config_of_soc();
|
||||||
|
|
||||||
if (!CONFIG(PICASSO_LPC_IOMUX))
|
if (!CONFIG(PICASSO_LPC_IOMUX))
|
||||||
cfg->sd_emmc_config = SD_EMMC_EMMC_HS400;
|
cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;
|
||||||
|
|
||||||
mainboard_program_gpios();
|
mainboard_program_gpios();
|
||||||
|
|
||||||
|
|
|
@ -7,7 +7,9 @@ chip soc/amd/picasso
|
||||||
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
|
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
|
||||||
register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
|
register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
|
||||||
|
|
||||||
register "sd_emmc_config" = "SD_EMMC_DISABLE"
|
register "emmc_config" = "{
|
||||||
|
.timing = SD_EMMC_DISABLE,
|
||||||
|
}"
|
||||||
|
|
||||||
register "has_usb2_phy_tune_params" = "1"
|
register "has_usb2_phy_tune_params" = "1"
|
||||||
|
|
||||||
|
|
|
@ -40,7 +40,9 @@ chip soc/amd/picasso
|
||||||
|
|
||||||
# End : OPN Performance Configuration
|
# End : OPN Performance Configuration
|
||||||
|
|
||||||
register "sd_emmc_config" = "SD_EMMC_EMMC_HS400"
|
register "emmc_config" = "{
|
||||||
|
.timing = SD_EMMC_EMMC_HS400,
|
||||||
|
}"
|
||||||
|
|
||||||
register "xhci0_force_gen1" = "0"
|
register "xhci0_force_gen1" = "0"
|
||||||
|
|
||||||
|
|
|
@ -40,7 +40,9 @@ chip soc/amd/picasso
|
||||||
|
|
||||||
# End : OPN Performance Configuration
|
# End : OPN Performance Configuration
|
||||||
|
|
||||||
register "sd_emmc_config" = "SD_EMMC_EMMC_HS400"
|
register "emmc_config" = "{
|
||||||
|
.timing = SD_EMMC_EMMC_HS400,
|
||||||
|
}"
|
||||||
|
|
||||||
register "xhci0_force_gen1" = "0"
|
register "xhci0_force_gen1" = "0"
|
||||||
|
|
||||||
|
|
|
@ -134,10 +134,10 @@ void variant_devtree_update(void)
|
||||||
* So we keep the speed low here, with the intent that
|
* So we keep the speed low here, with the intent that
|
||||||
* other variants implement these corrections.
|
* other variants implement these corrections.
|
||||||
*/
|
*/
|
||||||
cfg->sd_emmc_config = SD_EMMC_EMMC_HS200;
|
cfg->emmc_config.timing = SD_EMMC_EMMC_HS200;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
cfg->sd_emmc_config = SD_EMMC_DISABLE;
|
cfg->emmc_config.timing = SD_EMMC_DISABLE;
|
||||||
}
|
}
|
||||||
|
|
||||||
update_audio_configuration();
|
update_audio_configuration();
|
||||||
|
|
|
@ -15,5 +15,5 @@ void variant_devtree_update(void)
|
||||||
* Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned.
|
* Enable eMMC if eMMC bit is set in FW_CONFIG or device is unprovisioned.
|
||||||
*/
|
*/
|
||||||
if (!(variant_has_emmc() || boot_is_factory_unprovisioned()))
|
if (!(variant_has_emmc() || boot_is_factory_unprovisioned()))
|
||||||
cfg->sd_emmc_config = SD_EMMC_DISABLE;
|
cfg->emmc_config.timing = SD_EMMC_DISABLE;
|
||||||
}
|
}
|
||||||
|
|
|
@ -126,20 +126,34 @@ struct soc_amd_picasso_config {
|
||||||
uint32_t telemetry_vddcr_soc_slope;
|
uint32_t telemetry_vddcr_soc_slope;
|
||||||
uint32_t telemetry_vddcr_soc_offset;
|
uint32_t telemetry_vddcr_soc_offset;
|
||||||
|
|
||||||
enum {
|
struct {
|
||||||
SD_EMMC_DISABLE,
|
/*
|
||||||
SD_EMMC_SD_LOW_SPEED,
|
* SDHCI doesn't directly support eMMC. There is an implicit mapping between
|
||||||
SD_EMMC_SD_HIGH_SPEED,
|
* eMMC timing modes and SDHCI UHS-I timing modes defined in the linux
|
||||||
SD_EMMC_SD_UHS_I_SDR_50,
|
* kernel.
|
||||||
SD_EMMC_SD_UHS_I_DDR_50,
|
*
|
||||||
SD_EMMC_SD_UHS_I_SDR_104,
|
* HS -> UHS_SDR12 (0x00)
|
||||||
SD_EMMC_EMMC_SDR_26,
|
* DDR52 -> UHS_DDR50 (0x04)
|
||||||
SD_EMMC_EMMC_SDR_52,
|
* HS200 -> UHS_SDR104 (0x03)
|
||||||
SD_EMMC_EMMC_DDR_52,
|
* HS400 -> NONE (0x05)
|
||||||
SD_EMMC_EMMC_HS200,
|
*
|
||||||
SD_EMMC_EMMC_HS400,
|
* The kernel driver uses a heuristic to determine if HS400 is supported.
|
||||||
SD_EMMC_EMMC_HS300,
|
*/
|
||||||
} sd_emmc_config;
|
enum {
|
||||||
|
SD_EMMC_DISABLE,
|
||||||
|
SD_EMMC_SD_LOW_SPEED,
|
||||||
|
SD_EMMC_SD_HIGH_SPEED,
|
||||||
|
SD_EMMC_SD_UHS_I_SDR_50,
|
||||||
|
SD_EMMC_SD_UHS_I_DDR_50,
|
||||||
|
SD_EMMC_SD_UHS_I_SDR_104,
|
||||||
|
SD_EMMC_EMMC_SDR_26,
|
||||||
|
SD_EMMC_EMMC_SDR_52,
|
||||||
|
SD_EMMC_EMMC_DDR_52,
|
||||||
|
SD_EMMC_EMMC_HS200,
|
||||||
|
SD_EMMC_EMMC_HS400,
|
||||||
|
SD_EMMC_EMMC_HS300,
|
||||||
|
} timing;
|
||||||
|
} emmc_config;
|
||||||
|
|
||||||
uint8_t xhci0_force_gen1;
|
uint8_t xhci0_force_gen1;
|
||||||
|
|
||||||
|
|
|
@ -13,7 +13,7 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
|
||||||
{
|
{
|
||||||
int val = SD_DISABLE;
|
int val = SD_DISABLE;
|
||||||
|
|
||||||
switch (cfg->sd_emmc_config) {
|
switch (cfg->emmc_config.timing) {
|
||||||
case SD_EMMC_DISABLE:
|
case SD_EMMC_DISABLE:
|
||||||
val = SD_DISABLE;
|
val = SD_DISABLE;
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Reference in a new issue