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soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method 

CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.

BUG=b:156530805
TEST=Built and booted to kernel.

Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
John Zhao 2020-05-19 11:10:21 -07:00 committed by Patrick Georgi
parent e6e9fa6ef9
commit 7d054bd38f
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/tigerlake/acpi/tcss.asl
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@ -45,10 +45,10 @@ Scope (\_SB)
} }
/* /*
* Define PCH ACPIBASE as an ACPI operating region. The base address can be * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be
* found in Device 31, Function 2, Offset 40h. * found in Device 31, Function 2, Offset 40h.
*/ */
OperationRegion (PMIO, SystemMemory, PCH_PWRM_BASE_ADDRESS, 0x80) OperationRegion (PMIO, SystemIO, ACPI_BASE_ADDRESS, 0x80)
Field (PMIO, ByteAcc, NoLock, Preserve) { Field (PMIO, ByteAcc, NoLock, Preserve) {
Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */ Offset(0x6C), /* 0x6C, General Purpose Event 0 Status [127:96] */
, 19, , 19,