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soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options

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Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The
BIOS needs to program VrPowerDeliverDesign configuration per platform
according to the platform capabilities to avoid incorrect
electrial/power parameters. This is only added for Cannon Lake.

Refer to document 599797 for more details.

Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Christian Walter 2020-05-06 09:18:37 +02:00 committed by Patrick Georgi
parent 9ea70c02cd
commit e6e9fa6ef9
2 changed files with 8 additions and 0 deletions
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4
src/soc/intel/cannonlake/chip.h
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@ -413,6 +413,10 @@ struct soc_intel_cannonlake_config {
uint8_t LanWakeFromDeepSx;
uint8_t WolEnableOverride;
#if !CONFIG(SOC_INTEL_COMETLAKE)
uint32_t VrPowerDeliveryDesign;
#endif
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,

4
src/soc/intel/cannonlake/fsp_params.c
View file

@ -459,6 +459,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
#endif
}
#if !CONFIG(SOC_INTEL_COMETLAKE)
params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign;
#endif
dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
params->PeiGraphicsPeimInit = 1;